A 0.4V 430nA Quiescent Current NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28nm CMOS

📋 论文概要

该论文提出了一种0.4V供电、430nA静态电流的NMOS数字低压差线性稳压器（LDO），通过NAND型模拟辅助环路实现快速瞬态响应，解决了超低功耗应用中传统数字LDO瞬态响应慢和静态电流大的问题。

💡 主要创新点

• 提出NAND型模拟辅助环路，在不增加静态电流的情况下显著提升瞬态响应速度
• 采用粗调与细调结合的移位寄存器架构，实现宽负载范围下的高效调节
• 在28nm CMOS工艺中实现0.4V超低电压工作，静态电流仅430nA

🏷 关键词

📄 原文摘要

University of Electronic Science and Technology of China, Chengdu, China 3 Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal the number of registers. The fine loop contains an 8b SR, controlling eight 1×size power switches. The coarse loop uses a 4b low SR and a 16b high SR with carry in/out between the two SRs. The low SR controls four 8×-size power switches and the high SR controls sixteen 32×-size power switches in the coarse loop. All the shift-register outputs go to the LSs to control the power stage in the 2×VDD domain. 1 2 Ultra-low-power fully-integrated voltage regulators with fast load-transient performance are highly attractive for low-power systems-on-a-chip (SoCs). In such systems, the digital units working in the subthreshold region are more sensitive to supply variations. The digital low-dropout regulator (DLDO) is more suitable for low-supply-voltage operation, as compared to an analog LDO

👥 作者与机构

Xiaofei Ma1,2, Yan Lu1, Rui P. Martins1,3, Qiang Li2

University of Macau, Macau, China