A 1.1mW 200kS/s Incremental ΔΣ ADC with a DR of 91.5dB Using Integrator Slicing for Dynamic Power Reduction

📋 论文概要

该论文提出了一种采用积分器切片技术的增量ΔΣ ADC，实现了动态功耗降低。在1.1mW功耗和200kS/s采样率下，达到了91.5dB的动态范围，适用于多通道传感器读出等需要高分辨率Nyquist率ADC的应用。

💡 主要创新点

• 提出积分器切片技术，通过动态调整积分器的工作状态来降低功耗，同时保持高分辨率性能。
• 实现了低功耗（1.1mW）与高动态范围（91.5dB）的平衡，适用于多通道传感器读出系统。

🏷 关键词

📄 原文摘要

Nyquist-rate ADCs with high resolution are needed in many applications where, for example, multiplexed operation is needed as for multichannel sensor readout. For various tasks such as averaging-based analysis or lock-in detection high linearity at the presence of very low noise is required. While SAR ADCs are known for high power efficiency, they often show limited effective resolutions and linearity unless oversampling, mismatch error shaping or calibration techniques are employed [1,2]. The state of the art in high-resolution ADC design is thus dominated by oversampled converters, and for Nyquist-rate operation a significant power penalty must be paid. Another candidate is the incremental Delta-Sigma (I-ΔΣ) ADC, which still exploits oversampling and noise-shaping, but which is a true Nyquist-rate converter by regularly resetting the internal integrators. In all implementations, the most

👥 作者与机构

Patrick Vogelmann, Michael Haas, Maurits Ortmanns

University of Ulm, Ulm, Germany