A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FOM of -246dB for IoT Applications in 65nm CMOS

📋 论文概要

该论文提出了一种用于物联网应用的低功耗分数-N全数字锁相环（ADPLL），采用10位隔离恒定斜率数字时间转换器（DTC），在65nm CMOS工艺中实现了0.98mW的功耗和-246dB的FOM，解决了低功耗与低相位噪声/杂散之间的权衡问题。

💡 主要创新点

• 提出了一种隔离恒定斜率DTC，通过隔离技术减少噪声耦合，实现高线性度。
• 采用参考倍频器优化功耗与抖动之间的权衡，在981μW功耗下实现535fs抖动和-56dBc带内分数杂散。
• 整体ADPLL架构在2.0-2.8GHz频率范围内实现了-246dB的FOM，适用于2.4GHz ISM频段物联网应用。

🏷 关键词

📄 原文摘要

ultra-lowpower (ULP) transceivers (TRX) will be key elements in a variety of short-range network applications. The RF PLL in a TRX needs a significant amount of power due to the phase noise and spurious requirement. Compared with the analog PLLs, an ADPLL is more advantageous in nm-CMOS technologies [1-6]. This paper presents a 2.0-to-2.8GHz 653μW fractional-N ADPLL that achieves -242dB FOM in 65nm CMOS for 2.4GHz ISM band applications. The best power-jitter trade-off is achieved at 981μW using a reference doubler with 535fs jitter and a -56dBc in-band fractional spur, which corresponds to a FOM of -246dB. Thanks to the proposed 10b isolated constant-slope DTC, this ADPLL breaks the -240dB FOM barrier of sub-mW fractional-N ADPLLs. Figure 15.1.1 shows the ADPLL architecture. For a low power operation, a 4b

👥 作者与机构

Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo,

Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, Japan In a world that has become increasingly connected by the Internet,