An N40 256K×44 Embedded RRAM Macro with SL-Precharge SA and Low-Voltage Current Limiter to Improve Read and Write Performance

📋 论文概要

该论文提出了一种采用40nm工艺的256K×44嵌入式RRAM宏单元，通过SL预充电读出放大器（SL-Precharge SA）和低压电流限制器（Low-Voltage Current Limiter）来改善读写性能，解决了RRAM读写操作中的速度和功耗问题。

💡 主要创新点

• 提出SL预充电读出放大器（SL-Precharge SA），通过预充电源线来加速读取操作并降低功耗。
• 引入低压电流限制器（Low-Voltage Current Limiter），在写入过程中限制电流以提升写入性能并减少功耗。

🏷 关键词

📄 原文摘要

due to the simplicity of the RRAM element (RE) and its compatibility with a logic process. A RRAM bit cell (Fig. 30.1.1) consists of an NMOS select transistor and a bipolar RE, which consists of a bottom electrode (BE), a transition metal-oxide file (Hi-K), a metal capping layer and a top electrode (TE). The memory cell operates as a 3-terminal device, including bit-line (BL), source-line (SL) and wordline (WL). BL is connecting to TE, SL is connecting to the source node of the select transistor and word-line (WL) is connecting to the gate of the select transistor. A common SL (CSL) architecture is adopted in this work. CSL allows two or more columns to share one source line. So that the column mux number for SL can be reduced, therefore macro area can be saved. In addition, SL can be

👥 作者与机构

Chung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng, Chih-Feng Li,

Chih-Yang Chang, Wei-Chi Chen, Yu-Der Chih, Tsung-Yung Jonathan Chang TSMC, Hsinchu, Taiwan RRAM is an attractive and low-cost memory structure for embedded applications