A 0.0056mm2 All-Digital MDLL Using Edge

📋 论文概要

该论文提出了一种全数字乘法延迟锁定环（MDLL），通过边缘再提取、双环VCO和块共享频率跟踪环路技术，在0.0056mm²面积和0.3mW功耗下实现了292fsrms抖动和-249dB FOM，解决了传统MDLL中频率跟踪环路面积和功耗大的问题。

💡 主要创新点

• 提出边缘再提取技术，有效降低输出抖动。
• 采用双环VCO结构，提升频率跟踪精度和稳定性。
• 设计块共享频率跟踪环路，大幅减小面积和功耗。

🏷 关键词

📄 原文摘要

292fsrms Jitter and -249dB FOM Shiheng Yang1, Jun Yin1, Pui-In Mak1, Rui P. Martins1,2 University of Macau, Macau, China Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Multiplying delay-locked loops (MDLL) and injection-locked clock multipliers (ILCM) have shown improved jitter performance in recent years [1-5], but their PLL-based frequency-tracking loops (FTLs) for securing performance against frequency and PVT variations are area and power hungry. In [1], the frequency (FOUT) is tracked by a replica-delay cell of the VCO, such that the intrinsic phase information is preserved under reference injection (REF-INJ). Regrettably an analog FTL is susceptible to noise and mismatch from the charge pump, demanding more area (loop filter: 0.01mm2) and power (charge pump: 0.8mW) to limit the in-band jitter deterioration. For the digital FTLs, using double REF-INJ and pulse-width comparison [2] can

👥 作者与机构

Re-Extraction, Dual-Ring VCOs and a 0.3mW, Block-Sharing Frequency Tracking Loop Achieving