A 112Gb/s PAM-4 Transmitter with 3-Tap FFE in 10nm CMOS

📋 论文概要

该论文提出了一种采用10nm CMOS工艺、支持112Gb/s PAM-4调制的发射机，集成了3抽头前馈均衡器（FFE），解决了超高速率下信号完整性和均衡挑战。

💡 主要创新点

• 采用3抽头FFE架构，在112Gb/s PAM-4速率下实现有效均衡，补偿信道损耗。
• 基于10nm先进CMOS工艺，实现超高速率与低功耗的平衡。

🏷 关键词

📄 原文摘要

infrastructure has fueled the industry to develop ultra-high-speed/density wireline links compliant with electrical interface standards such as CEI-56G and 802.3bs400GbE. Recent publications have demonstrated CMOS transmitters (TX) operating from 50-64Gb/s [1-4], and early planning for the next generation of 100Gb/s+ wireline standards is underway. Long-reach wireline standards at 56Gb/s have largely adopted a PAM-4 modulation scheme that maintains the same symbol rate as the previous generation of 28Gb/s NRZ transceivers. For 112Gb/s transceivers, however, higher order modulation (e.g., PAM-8/16) is unlikely to be adopted due to the tradeoff in SNR and backward compatibility. Therefore, the symbol rate for 112Gb/s PAM-4 must be doubled relative to the previous

👥 作者与机构

Jihwan Kim, Ajay Balankutty, Rajeev Dokania, Amr Elshazly,

Hyung Seok Kim, Sandipan Kundu, Skyler Weaver, Kai Yu, Frank O'Mahony Intel, Hillsboro, OR The rapidly growing demand for high-bandwidth data communication