A 0.01mm2 4.6-to-5.6GHz Sub-Sampling Type-I Frequency Synthesizer with –254dB FOM

📋 论文概要

该论文提出了一种采用亚采样技术的Type-I频率合成器，实现了0.01mm²的超小芯片面积、4.6-5.6GHz的频率范围和-254dB的FOM，解决了传统Type-II电荷泵PLL中功耗、噪声和面积难以同时优化的难题。

💡 主要创新点

• 采用亚采样Type-I架构，无需大环路滤波器电容，显著减小芯片面积至0.01mm²。
• 通过优化VCO和亚采样鉴相器设计，在低功耗下实现了-254dB的优异FOM性能。

🏷 关键词

📄 原文摘要

Power consumption, Performance in terms of phase noise and integrated jitter, and Area (PPA) are three design metrics that have driven countless research efforts in CMOS frequency-synthesizer design. Design limitations and systemlevel tradeoffs have made simultaneous optimizations of PPA metrics in PLLs challenging. In traditional Type-II charge-pump (CP) based PLLs, power is consumed in the VCO, divider (N), and CP to improve noise performance, and area is consumed in large loop-filter (LF) capacitors. ADPLLs are attractive due to compact LF, but are limited in noise performance. Sub-sampling (SS) PLLs eliminate divider noise, and remove the N2 amplification of the phase detector (PD), CP, and LF noise, thereby improving the overall phase-noise performance

👥 作者与机构

Ahmad Sharkia, Shahriar Mirabbasi, Sudip Shekhar

University of British Columbia, Vancouver, Canada