A 36.3-to-38.2GHz -216dBc/Hz2 40nm CMOS Fractional-N FMCW Chirp Synthesizer PLL with a Continuous-Time Bandpass Delta-Sigma Time-to-Digital Converter rotation allows us to emulate the divider-ratio step size of 8/32 = 1/4. Since the phase rotation occurs ahead of the final divider stage, we perform only one phase shift per divider output cycle to retain the step size of 1/4 for the entire divider chain. A 2nd-order ΔΣ modulator controls the phase rotation for fractional-N division. Finally, on-chip chirp control logic modulates the PLL division ratio to generate the desired FMCW waveform profile.

📋 论文概要

本文提出一种40nm CMOS的36.3-38.2GHz分数-N FMCW Chirp合成器PLL，采用连续时间带通ΔΣ调制器实现噪声整形，解决了毫米波全数字PLL中传统TDC性能受限的问题，达到-216dBc/Hz^2的低相位噪声。

💡 主要创新点

• 采用连续时间带通ΔΣ调制器替代传统TDC，实现噪声整形，降低相位噪声。
• 实现36.3-38.2GHz分数-N FMCW Chirp合成，适用于汽车雷达等毫米波应用。
• 在40nm CMOS工艺下实现整体设计，无需大量校准即可获得高性能。

📄 原文摘要

Broadcom, Irvine, CA 1 Automotive radar and other mm-wave applications require high-quality frequency synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the mm-wave range, but all-digital PLLs (ADPLLs) promise greater flexibility and area efficiency. However, existing mm-wave ADPLLs are large, fail to offer low in-band phase noise [1] or must rely on extensive calibration [2]. Performance limitations of conventional TDCs still remain a major roadblock for the adoption of high-frequency ADPLLs. To address this problem, this work introduces a noise-shaping TDC based on a 4th-order bandpass ΔΣ modulator (BPDSM) to achieve low integrated noise (183fsrms) and high linearity. Our approach enables low in-band phase noise (-85dBc/Hz @ 100kHz) for wide loop bandwidths (>1MHz) in a calibration-free single-loop digital 36.3-to-38.2GHz PLL. The prototype PLL effectively generates fast (500MHz/55μs) and precise

👥 作者与机构

Daniel Weyer1, M. Batuhan Dayanik2, Sunmin Jang1, Michael P. Flynn1

University of Michigan, Ann Arbor, MI