A Fully Adaptive 19-to-56Gb/s PAM-4 Wireline Transceiver with a Configurable ADC in 16nm FinFET

📋 论文概要

本文提出了一款采用16nm FinFET工艺的全自适应19-56Gb/s PAM-4有线收发器，通过可配置ADC和先进均衡技术支持50G/100G/400G端口，旨在降低基础设施升级成本。

💡 主要创新点

• 实现19-56Gb/s宽速率范围的全自适应PAM-4收发，无需外部校准
• 采用可配置ADC架构，灵活支持不同速率和调制方式
• 结合前向纠错（FEC）进一步提升链路性能，兼容现有通道

🏷 关键词

📄 原文摘要

Arianne Roldan2, Wenfeng Zhang1, Jin Namkoong1, Toan Pham1, Bruce Xu1, Winson Lin1, Hongtao Zhang1, Nakul Narang2, Kee Hian Tan2, Geoff Zhang1, Yohan Frans1, Ken Chang1 Xilinx, San Jose, CA Xilinx, Singapore, Singapore 1 2 Trends in IoT and cloud computing continue to accelerate bandwidth demand, requiring technology innovation to cover 50G, 100G and 400G ports without significant increase in cost or power per bit. In order to mitigate the cost of infrastructure upgrade, the industry has proposed a standard for 56Gb/s PAM-4 interfaces [1] that can support legacy channels using Forward Error Correction (FEC). Recent publications achieve good pre-FEC BER performance using ADCbased receivers [2,3], but the power consumption (e.g. >550mW per lane at 56Gb/s excluding DSP/digital power in [2]) could be prohibitive for products with large numbers of transceivers. This paper demonstrates a fully integrated and

👥 作者与机构

Parag Upadhyaya1, Chi Fung Poon1, Siok Wei Lim2, Junho Cho1,