Wireline I/O

Naohiro Kohmu1, Fumio Yuki1, Norio Nakajima2, Takashi Muto2, Junya Nasu2, Takemasa Komori2, Hideki Koba2, Tatsunori Usugi2, Tomofumi Hokari2, Tsuneo Kawamata2, Yuichi Ito2, Seiichi Umai2, Masatoshi Tsuge2, Takeo Yamashit

introduced in recent years for next generation wireline communication systems for more efficient use of the available link bandwidth. High-speed ADCs with digital signal processing (DSP) can provide robust performance fo

Thomas Toifl2, Yong Liu3, Ankur Agrawal1, Peter Buchmann2, Alexander Rylyakov4, Michael Beakes1, Benjamin Parker1, Mounir Meghelli1 IBM T. J. Watson Reseach Center, Yorktown Heights, NY, IBM Zurich Research Laboratory, R

Reaching a power efficiency of 1mW/Gb/s has proven difficult for wireline transceivers operating at tens of gigabits per second. At 40Gb/s, recent receivers consume from 150mW [1] to 1W [2]. This paper describes a receiv

I/O receivers routinely equalize ISI over 10 or more post-cursor UI. IIR DFEs are a low-power technique for canceling long post-cursor ISI tails, and have been demonstrated compensating over 20dB loss at fbit/2 up to 10G

Marcel Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl IBM Zurich Research Laboratory, Rüshlikon, Switzerland The demand for energy-efficient I/O link transceive

Schwarz, Munich, Germany, 4 Finisar, Berlin, Germany, 5TU Berlin, Berlin, Germany 1 2 Long-haul optical links are experiencing a transition to coherent techniques because they enable the use of modulation techniques with

STMicroelectronics, Pavia, Italy, 2University of Pavia, Pavia, Italy 1 The ever-increasing data center IP traffic, up to 8.6 zettabytes per year by 2018 with nearly 3× growth since 2013 [1], requires power-efficient high

Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong Samsung Semiconductor, San Jose, CA The continuous increase in the resolution, color depth and refresh rate

Proximity communication offers the convenience of a connector-less high-speed interface using energy-efficient mixed-signal transceivers [1-4]. Such interfaces are attractive for ultra-thin handheld/mobile devices with z

Seong-Joong Kim, Mrunmay Talegaonkar, Romesh Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu University of Illinois, Urbana-Champaign, IL Dynamic voltage and frequency scaling (DVFS) [1] and burst-mode

key challenge in multiple applications, from high-data-rate I/O to reconfigurable radio and radar. Conventional wireline and wireless LC-VCO based PLLs can cover a large tuning range using multiple frequency bands [1, 2]

An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency clocks, using a limited budget in terms of silicon area and power consumption. However, an

A low-spur PLL is desirable for many applications since it avoides mixing unwanted blocker signals, prevents emission mask violations or minimizes jitter in the clock source. Internal spurs result from the nature of PLL

Jacob Wysocki2, Koki Uchino1, Yoshifumi Miyajima3, Yosuke Ueno1, Kenichi Maruko1, Zhiwei Zhou1, Hideyuki Matsumoto1, Hideyuki Suzuki1, Norio Shoji1 Sony, Tokyo, Japan, Mixed Signal Systems, Scotts Valley, CA, 3 Sony LSI

Karthik Swaminathan2, Ramalingam Pandarinathan2, Ramesh Pasagadugula2, VamshiKrishna Yakkala2, Mostafa Hammad1, Karim Abdelhalim1, Kaijun Li1, Su Cui1, Jing Wang1, Ahmad Chini1, Mehmet Tazebay1, Suresh Venkatesan2, Derek

Jieqiong Du1, Po-Tsang Huang1,2, Sheau Jiung Lee1, Huan-Neng Chen3, Chewn-Pu Jou3, Fu-Lung Hsueh3, Mau-Chung Frank Chang1,2 University of California, Los Angeles, CA, National Chiao Tung University, Hsinchu, Taiwan, 3 TS

Brian Holden1, Ali Hormati1, Peter Hunt2, Margaret Johnston1, John Keay2, Sergio Pesenti1, Richard Simpson2, David Stauffer1, Andrew Stewart2, Giuseppe Surace2, Armin Tajalli1, Omid Talebi Amiri1, Anton Tschank2, Roger U

greatly reduce power in serial link transceivers. Ideally, power efficiency at a given data rate can be improved by reducing VDD while increasing the number of multiplexed circuits operating in parallel at lower clock fr

in 65nm CMOS Tejasvi Anand1, Mrunmay Talegaonkar1, Ahmed Elkholy1, Saurabh Saxena1, Amr Elshazly2, Pavan Kumar Hanumolu1 University of Illinois, Urbana, IL, 2Intel, Hillsboro, OR 1 Energy-proportional operation of serial

Sebastian Hoyos, Samuel Palermo control that allows all combinations ranging from all pre-cursor to all postcursor equalization taps. A loop-unrolled architecture is utilized to meet the critical feedback timing paths of

to data-rates of 40Gb/s and beyond. Most previous standards for these networking applications use NRZ signaling. However, practical signal integrity constraints have led to a renewed interest in also supporting PAM4 for

signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more severe and do not benefit from pr

Bruce Xu, Daniel Wu, Didem Turker, Hesam Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang Xilinx, San Jose, CA The introduction of high-speed backplane transceivers inside

Norio Nakajima2, Masatoshi Tsuge2, Tatsunori Usugi2, Tomofumi Hokari2, Hideki Koba2, Takemasa Komori2, Junya Nasu2, Tsuneo Kawamata2, Yuichi Ito2, Seiichi Umai2, Jun Kumazawa2, Hiroaki Kurahashi2, Takashi Muto2, Takeo Ya

in metro networks and data centers and pushed the serial link data rate into 25Gb/s territory, populated by such electrical interface as OIF CEI-25G, CEI-28G [1], IEEE 802.3bj 100G-KR4. To cope with severe channel impair

University of Pavia, Pavia, Italy, STMicroelectronics, Pavia, Italy 1 2 Data centers and high-performance computing markets are growing at a fast pace, mandating power-efficient and cost-effective high-speed interconnect

and high-density interconnects because of the high-bandwidth and low-crosstalk properties of optical signals. The next challenge for optical interconnects is to move to a serial data-rate of 25Gb/s or higher [1,2]. To ac

power, high-density, multilane links with a data rate exceeding 25Gb/s/lane are needed. An optical transceiver with a retiming capability would significantly enhance the usability of the link by extending the reach. Such

Ayman Shafik3, Nan Qi1, Yang Liu5, Ran Ding5, Tom Baehr-Jones5, Marco Fiorentino4, Michael Hochberg5, Samuel Palermo3, Patrick Yin Chiang1,6 Oregon State University, Corvallis, OR, 2University of Delaware, Newark, DE, Te

Peter Verheyen1, Mark Ingels1, Hongtao Chen1,3, Jeroen De Coster1, Guy Lepage1, Brad Snyder1, Kristin De Meyer1,2, Michiel Steyaert2, Nicola Pavarelli4, Jun Su Lee4, Peter O’Brien4, Philippe Absil1, Joris Van Campenhout1

Binhao Wang1, Zhongkai Wang4, Rui Bai2, Chin-Hui Chen3, Marco Fiorentino3, Patrick Yin Chiang2,4, Samuel Palermo1 Texas A&M University, College Station, TX, Oregon State University, Corvallis, OR, 3 Hewlett-Packard Labs,

Modern SoC systems impose stringent requirements on on-chip clock generation and distribution. Ring-oscillator (RO) based injection-locked (IL) clocking has been used in the past [1] to provide a low-power, low-area and

Tomoyuki Akiyama1,3,4, Shigeaki Sekiguchi1,3,4, Hiroji Ebe1,3,4, Nobuhiro Imaizumi1, Tomoyuki Akahoshi1, Suguru Akiyama3, Shinsuke Tanaka3, Takasi Simoyama3, Ken Morito1,3,4, Takuji Yamamoto2, Toshihiko Mori1, Yoichi Koy

John Bulzacchelli, Abhijeet Ardey, Benjamin Parker, Michael Beakes, Chris Baks, Clint Schow, Mounir Meghelli IBM Research, Yorktown Heights, NY Rapidly reconfigurable optical networks that keep the data in the optical do

as in reconfigurable radio and radar applications, is the generation of a clean clock signal supporting a wide range of frequencies. The introduction of fractional-N synthesis capability for wide-tuning-range application

Ring PLLs play an important role in mobile baseband applications. In cases where fine frequency resolution and low jitter are both needed, wideband fractional-N PLL architectures with quantization noise (Q-noise) cancell

University of Illinois, Urbana, IL Sub-harmonically injection locked oscillators provide a simple means for generating very-low-noise high-frequency clocks in a power, and area efficient manner [1-5]. Ideally, a free-run

Christian Menolfi, Marcel Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu IBM Zurich, Rüschlikon, Switzerland We report the implementation of a continuous-time linear eq

links integrated in advanced CMOS are ubiquitous in modern microprocessor systems. These commodity links have fixed performance specs and therefore realize the benefit of technology scaling in area and power reduction at

precursor shape and main cursor peak level. The summing integrator then sums and integrates the duobinary equalizer output and signals from DFE taps to generate a duobinary signal free of ISI and high-frequency noise. Th

Advancements in CMOS technology have enabled exponential growth of computational power. However, data processing efficiency also relies on sufficient data communication bandwidth between different units of a computing sy

Technology scaling has enabled RF-CMOS circuits that operate in the millimeterwave frequency range (30 to 300GHz) where large bandwidths are available. These bandwidths can be exploited to increase data-rates of wireless

Modular smart phones have been attracting attention (Fig. 10.1.1) because users can freely customize their phones by purchasing modules and assembling them

high-performance computing systems and data centers are currently being developed. The transmission range of conventional electrical interconnections is limited due to the bandwidth of electrical channels. VCSEL-based op

Broadcom, Irvine, CA 1 2 As an alternative to the conventional dual-loop architecture, reference-less CDR architectures have become more popular in industry because of their simplicity and flexibility [1-5]. However, the

standalone PHY chips with hundreds of millions of ports shipped every year. Transceiver design has recently focused on power reduction driven by the need for higher port density and throughput with minimum energy and the

Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M.L. van der Goes, Klaas Bult Broadcom, Bunnik, The Netherlands The IEEE802.3an 10GBASE-T standard describes full-duplex 10Gb/s Ethernet transmission over four

high-performance computing systems require high-bandwidth serial links to transport high-speed data streams among computational blocks. Optical links have recently attracted attention due to their low channel loss at hig

cost-effective fiber for high-speed LANs. Modal dispersion leads to optical-energy spreading over several symbol periods, drastically limiting distance and data-rate. Compared with copper channels, equalization is challe