Continuous-Time Linear Equalization with Programmable Active-Peaking Transistor Arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap Speculative DFE Receiver

📋 论文概要

该论文在14nm FinFET工艺中实现了一种连续时间线性均衡器(CTLE)，采用可编程有源峰值晶体管阵列来控制高频增益峰化，并高效接口到电流求和级（用于决策反馈均衡器的系数叠加），实现了16Gb/s的数据速率和2mW/Gb/s的功耗效率。

💡 主要创新点

• 提出可编程有源峰值晶体管阵列，通过调节晶体管偏置实现CTLE高频增益峰值的灵活控制。
• 设计CTLE与电流求和级的接口，支持DFE系数的线性模拟叠加，适用于多路交错结构。

🏷 关键词

📄 原文摘要

Christian Menolfi, Marcel Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu IBM Zurich, Rüschlikon, Switzerland We report the implementation of a continuous-time linear equalizer (CTLE) featuring a new technique to control the high-frequency gain peaking and to interface to current-summing stages usually implemented as interleaved slices for the linear analog superposition of the coefficients of decision-feedback equalizers (DFE). The circuits are implemented in 14nm FinFET SOI CMOS technology and are included in a prototype receiver targeted to 16Gb/s serial I/O links for multi-core microprocessors off-chip communication. The architecture is shown in Fig. 10.6.1. Power efficiency and compactness are among the primary goals of the study together with an equalization capability sufficient to recover at bit-error rate (BER) levels below 10-12 data transmitted across smooth

👥 作者与机构

Pier Andrea Francese, Thomas Toifl, Matthias Braendli,