ISSCC 2015
Session 1
Plenary
Silicon Technologies and Solutions for the Data-Driven World Kinam Kim
The remarkable evolution of human society over the centuries has been driven by information. As information became digitalized thanks to silicon technologies, creating, sharing, and searching of data have become much eas
ISSCC 2015
Session 1
Plenary
The Future of IC Design Innovation Sehat Sutardja
One of the greatest achievements of human kind is undoubtedly its ability to build tiny machines that marry the functionalities of computers and wireless communication devices so cheaply that almost anyone in the world c
ISSCC 2015
Session 1
Plenary
Analog CMOS from 5 Micrometer to 5 Nanometer Willy Sansen
The most important application of ICs, today, is most probably the Internet-ofThings. It involves sensor nodes and communications at the lowest-possible power levels. Similar low power levels are required for the next-ge
ISSCC 2015
Session 10
Wireline I/O
A 6Gb/s 6pJ/b 5mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission-Line Coupler and EMC-Qualified Pulse Transceiver
Modular smart phones have been attracting attention (Fig. 10.1.1) because users can freely customize their phones by purchasing modules and assembling them
ISSCC 2015
Session 10
Wireline I/O
An FSK Plastic Waveguide Communication Link in 40nm CMOS
Technology scaling has enabled RF-CMOS circuits that operate in the millimeterwave frequency range (30 to 300GHz) where large bandwidths are available. These bandwidths can be exploited to increase data-rates of wireless
ISSCC 2015
Session 10
Wireline I/O
A 7.5mW 7.5Gb/s Mixed NRZ/Multi-Tone Serial-Data Transceiver for Multi-Drop Memory Interfaces in 40nm CMOS
Advancements in CMOS technology have enabled exponential growth of computational power. However, data processing efficiency also relies on sufficient data communication bandwidth between different units of a computing sy
ISSCC 2015
Session 10
Wireline I/O
A 5.8Gb/s Adaptive Integrating Duobinary-Based DFE Receiver for Multi-Drop Memory Interface
precursor shape and main cursor peak level. The summing integrator then sums and integrates the duobinary equalizer output and signals from DFE taps to generate a duobinary signal free of ISI and high-frequency noise. Th
ISSCC 2015
Session 10
Wireline I/O
A 5.9pJ/b 10Gb/s Serial Link with Unequalized MM-CDR in 14nm Tri-Gate CMOS
links integrated in advanced CMOS are ubiquitous in modern microprocessor systems. These commodity links have fixed performance specs and therefore realize the benefit of technology scaling in area and power reduction at
ISSCC 2015
Session 10
Wireline I/O
Continuous-Time Linear Equalization with Programmable Active-Peaking Transistor Arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap Speculative DFE Receiver
Christian Menolfi, Marcel Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu IBM Zurich, Rüschlikon, Switzerland We report the implementation of a continuous-time linear eq
ISSCC 2015
Session 10
Wireline I/O
A 6.75-to-8.25GHz 2.25mW 190fsrms Integrated-Jitter PVT-Insensitive Injection-Locked Clock Multiplier Using All-Digital Continuous Frequency-Tracking Loop in 65nm CMOS
University of Illinois, Urbana, IL Sub-harmonically injection locked oscillators provide a simple means for generating very-low-noise high-frequency clocks in a power, and area efficient manner [1-5]. Ideally, a free-run
ISSCC 2015
Session 10
Wireline I/O
A Wideband Fractional-N Ring PLL Using a NearGround Pre-Distorted Switched-Capacitor Loop Filter
Ring PLLs play an important role in mobile baseband applications. In cases where fine frequency resolution and low jitter are both needed, wideband fractional-N PLL architectures with quantization noise (Q-noise) cancell
ISSCC 2015
Session 10
Wireline I/O
A 13.1-to-28GHz Fractional-N PLL in 32nm SOI CMOS with a ΔΣ Noise-Cancellation Scheme
as in reconfigurable radio and radar applications, is the generation of a clean clock signal supporting a wide range of frequencies. The introduction of fractional-N synthesis capability for wide-tuning-range application
ISSCC 2015
Session 11
Image Sensors
A Time-Divided Spread-Spectrum Code Based 15pW-Detectable Multi-Channel fNIRS IC for Portable Functional Brain Imaging
degenerative brain diseases, such as stroke and Alzheimer’s disease, is rapidly increasing. It is imperative for those suffering from such slow progressing and recurring brain diseases to continuously monitor and manage
ISSCC 2015
Session 11
Image Sensors
A 10.8ps-Time-Resolution 256×512 Image Sensor with 2-Tap True-CDS Lock-In Pixels for Fluorescence Lifetime Imaging
Taishi Takasawa1, Yoshimasa Kawata1, Nobukazu Teranishi1, Zhuo Li1, Izhal Abdul Halin2, Shoji Kawahito1 Shizuoka University, Hamamatsu, Japan Putra University, Selangor Darul Ehsan, Malaysia 1 2 Fluorescence lifetime ima
ISSCC 2015
Session 11
Image Sensors
A 160×120-Pixel Analog-Counting Single-Photon Imager With Sub-ns Time-Gating and Self-Referenced Column-Parallel A/D Conversion for Fluorescence Lifetime Imaging
image sensors able to gather information about photon position, number and time distribution, enabling cost-effective devices for scientific imaging applications like fluorescence lifetime imaging microscopy (FLIM), Rama
ISSCC 2015
Session 11
Image Sensors
A Time-Correlated Single-Photon-Counting Sensor with 14GS/s Histogramming Time-to-Digital Converter
Andrew J. Holmes2, Bruce Rae2, Lindsay A. Grant2, Robert K. Henderson1 University of Edinburgh, Edinburgh, United Kingdom, 2 STMicroelectronics, Edinburgh, United Kingdom 1 Time-correlated single photon counting (TCSPC)
ISSCC 2015
Session 11
Image Sensors
A Multi-Channel Neural-Recording Amplifier System with 90dB CMRR Employing CMOS-Inverter-Based OTAs with CMFB Through Supply Rails in 65nm CMOS
In addition to minimizing input-referred noise and lowering power consumption, a good multi-channel neural amplifier system should be able to significantly reject common-mode electrical interference (CMI). The dominant s
ISSCC 2015
Session 11
Image Sensors
A Multimodality CMOS Sensor Array for Cell-Based Assay and Drug Screening
tissue-specific physiological behaviors under external biochemical stimuli. External biochemical stimuli trigger endogenous cellular mechanisms that produce a cascade of physiological changes, resulting in easily measura
ISSCC 2015
Session 11
Image Sensors
Integrated Ultrasonic System for Measuring Body-Fat Composition
solution for accurate assessment of body fat is presented that addresses a growing consumer interest in economical and easy-to-use solutions for monitoring personal health and fitness. Unlike the prevalent present soluti
ISSCC 2015
Session 12
Power Management
A 0.518mm2 Quasi-Current-Mode Hysteretic Buck DC-DC Converter with 3µs Load Transient Response in 0.35µm BCDMOS
to integrate more DC-DC converters into the power-management IC. Consequently, there is a growing need for an area-efficient and simple controller design for DC-DC converters. A simple hysteretic control without any addi
ISSCC 2015
Session 12
Power Management
A 1.8V 30-to-70MHz 87% Peak-Efficiency 0.32mm2 4-Phase Time-Based Buck Converter Consuming 3µA/MHz Quiescent Current in 65nm CMOS
in terms of high output power, low ripple, fast load transient response, high efficiency across a very wide range of load currents, and alleviated output filter requirements. However, the need for complex controllers tha
ISSCC 2015
Session 12
Power Management
PWM Buck Converter with >80% PCE in 45µA-to-4mA Loads Using Analog-Digital Hybrid Control for Implantable Biomedical Systems
Implantable biomedical systems usually operate in energy-limited environments and exhibit large variation of power consumption ranging from constant lowpower (bio-signal sensing) to sporadic high-power (stimulation and/o
ISSCC 2015
Session 12
Power Management
A 7.5W-Output-Power 96%-Efficiency Capacitor-Free Single-Inductor 4-Channel All-Digital Integrated DC-DC LED Driver in a 0.18µm Technology
semiconductor-based systems. It is expected that solid-state lighting (SSL) will dominate general lighting in the near future. Two main challenges that must be met in SSL are the reduction of the bill of materials (BOM),
ISSCC 2015
Session 12
Power Management
An Error-Based Controlled Single-Inductor 10-Output DC-DC Buck Converter with High Efficiency at Light Load Using Adaptive Pulse Modulation
very important issue for Power-Management ICs (PMICs). Single-Inductor Multiple-Output (SIMO) converters are excellent candidates to meet this requirement [1-3]. However, there are several issues with SIMO converters, su
ISSCC 2015
Session 12
Power Management
90% Peak Efficiency Single-Inductor-Multiple-Output DC-DC Buck Converter with Output Independent Gate Drive Control
Shin-Hao Chen1, Ting-Jung Lo1, Ke-Horng Chen1, Chin-Long Wey1, Ying-Hsi Lin2, Chao-Cheng Lee2, Jian-Ru Lin2, Tsung-Yen Tsai2 National Chiao Tung University, Hsinchu, Taiwan, Realtek Semiconductor, Hsinchu, Taiwan 1 2 Sin
ISSCC 2015
Session 12
Power Management
A Power-Management ASIC with Q-Modulation Capability for Efficient Inductive Power Transmission
Georgia Institute of Technology, Atlanta, GA 1 2 A wide variety of applications can benefit from near-field wireless power transfer using coupled inductive links, such as wireless sensors and implantable microelectronic
ISSCC 2015
Session 12
Power Management
Wireless Power Transfer System Using Primary Equalizer for Coupling- and Load-Range Extension in Bio-Implant Applications
Wireless power transfer (WPT) in the range of 10 to 100mW [1] is widely used in implantable medical devices (IMDs) to eliminate the use of a battery. Due to load and coupling variations, the output voltage of the rectifi
ISSCC 2015
Session 12
Power Management
A Fully Integrated 6W Wireless Power Receiver Operating at 6.78MHz with Magnetic Resonance Coupling
of Technology, Atlanta, GA 1 3 Wireless power transfer (WPT) systems are becoming ubiquitous with applications in powering medical implants and a range of portable consumer electronic devices such as smart phones and wea
ISSCC 2015
Session 13
RF & Wireless
A 227pJ/b -83dBm 2.4GHz Multi-Channel OOK Receiver Adopting Receiver-Based FLL
The OOK demodulator and symbol timing-recovery circuits convert the ED output into final digital bit streams. In Fig. 13.1.2, for the incoming OOK signal, the initial tuning for the VCO frequency is done by the AFC. The
ISSCC 2015
Session 13
RF & Wireless
A 3.7mW-RX 4.4mW-TX Fully Integrated Bluetooth Low-Energy/IEEE802.15.4/Proprietary SoC with an ADPLL-Based Fast Frequency Offset Compensation in 40nm CMOS
Ao Ba1, Benjamin Busze1, Ming Ding1, Pieter Harpe2, Gert-Jan van Schaik1, Georgios Selimis1, Hans Giesen1, Jordy Gloudemans1, Adnane Sbai1, Li Huang1, Hiromu Kato3, Guido Dolmans1, Kathleen Philips1, Harmke de Groot1 Hol
ISSCC 2015
Session 13
RF & Wireless
A 10mW Bluetooth Low-Energy Transceiver with On-Chip Matching
Rahul Todi, William Aartsen, Wim Kruiskamp, Johan Haanstra, Enno Opbroek, Søren Rievers, Peter Seesink, Harrie Woering, Chris Smit Dialog Semiconductor, 's-Hertogenbosch, The Netherlands Wireless sensor nodes present a d
ISSCC 2015
Session 13
RF & Wireless
A 6.3mW BLE Transceiver Embedded RX ImageRejection Filter and TX Harmonic-Suppression Filter Reusing On-Chip Matching Network
Kenichi Shibata2, Kenji Toyota2, Tatsuhito Saitou3, Hisayasu Sato1, Koichi Yahagi2, Yoshihiro Hayashi4 Renesas Electronics, Itami, Japan, 2Renesas Electronics, Kawasaki, Japan, Renesas System Design, Kawasaki, Japan, 4 R
ISSCC 2015
Session 13
RF & Wireless
A -97dBm-Sensitivity Interferer-Resilient 2.4GHz Wake-Up Receiver Using Dual-IF Multi-N-Path Architecture in 65nm CMOS
University of Lille, Lille, France 1 3 Wake-up receivers are considered as practical solutions to enable ultra-lowpower (ULP) wireless sensor nodes (WSN) in a dense environment. A low data-rate (<~50kb/s) wake-up receive
ISSCC 2015
Session 13
RF & Wireless
A 600μW Bluetooth Low-Energy Front-End Receiver in 0.13μm CMOS Technology
*Now at Qualcomm, San Diego, CA One of the main goals for the next generation of radios for wireless sensor and body-area networks (WSN and WBAN) is a sub-mW receiver (RX) compliant with energy-harvested supplies. In thi
ISSCC 2015
Session 13
RF & Wireless
A +10dBm 2.4GHz Transmitter with sub-400pW Leakage and 43.7% System Efficiency
Extreme energy constraints inherent in many exciting new wireless sensing applications (such as [1-3]) virtually dictate that such systems operate with extremely low duty cycles, harvesting and storing energy over long p
ISSCC 2015
Session 13
RF & Wireless
A 5.8GHz RF-Powered Transceiver with a 113μW 32-QAM Transmitter Employing the IF-based Quadrature Backscattering Technique
network (WSN) application would deeply exacerbate the spectral congestion issue, RF-powered sensor nodes [1,2] still support only low spectral-efficiency modulation such as OOK. State-of-the-art standard-compliant RF tra
ISSCC 2015
Session 14
Digital Processors
A 0.048mm2 3mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique
Systems-onChip (SoCs), which contain microprocessors, I/O interfaces, memories, power management, and communication systems. Fully synthesizable PLLs [1-2], designed using a pure digital design flow, have been proposed t
ISSCC 2015
Session 14
Digital Processors
A Physically Unclonable Function with BER <10-8 for Robust Chip Authentication Using Oscillator Collapse in 40nm CMOS
Security is a key concern in today’s mobile devices and a number of hardware implementations of security primitives have been proposed, including true random number generators, differential power attack avoidance, and ch
ISSCC 2015
Session 14
Digital Processors
15fJ/b Static Physically Unclonable Functions for Secure Chip Identification with <2% Native Bit Instability and 140× Inter/Intra PUF Hamming Distance Separation in 65nm
Physically unclonable functions (PUFs) enable information security down to the chip level [1-4]. Arrays of PUF bitcells (Fig. 14.3.1) generate chip-specific keys that are unpredictable, repeatable and cannot be measured
ISSCC 2015
Session 14
Digital Processors
A 5GHz -95dBc-Reference-Spur 9.5mW Digital Fractional-N PLL Using Reference-Multiplied Time-to-Digital Converter and Reference-Spur Cancellation in 65nm CMOS
proposed for a low-power, low-noise fractional-N frequency synthesizer. Among the various innovations, a reference-multiplied architecture offers distinct advantages compared to conventional DPLLs [1]. First, low quantiz
ISSCC 2015
Session 14
Digital Processors
A 1.22ps Integrated-Jitter 0.25-to-4GHz Fractional-N ADPLL in 16nm FinFET CMOS
(ADPLLs) offer faster locking time, easier portability and better performance in advanced semiconductor processes as compared to analog PLLs. Advanced FinFET devices exhibit better gm and ION than planar devices [1], but
ISSCC 2015
Session 14
Digital Processors
An All-Digital Power-Delivery Monitor for Analysis of a 28nm Dual-Core ARM Cortex-A57 Cluster
ARM, Cambridge, United Kingdom The current trend for System-on-Chip (SoC) compute subsystems is to improve energy efficiency, while operating at a similar power budget as previous generations. Reduced supply voltages and
ISSCC 2015
Session 14
Digital Processors
In-Situ Techniques for In-Field Sensing of NBTI Degradation in an SRAM Register File
SRAM register files have sensitive circuitry and often operate with high switching activity and at high temperature. This makes them particularly vulnerable to aging by negative-bias temperature instability (NBTI) degrad
ISSCC 2015
Session 14
Digital Processors
A 0.009mm2 2.06mW 32-to-2000MHz 2nd-Order ΔΣ Analogous Bang-Bang Digital PLL with Feed-Forward Delay-Locked and Phase-Locked Operations in 14nm FinFET Technology
architectures, from a planar structure to a FinFET to achieve decreased leakage, further downscaling, and better sub-threshold slope, even under a lower power supply [1]. Downscaling trends have forced the analog semicon
ISSCC 2015
Session 14
Digital Processors
A Sub-Sampling All-Digital Fractional-N Frequency Synthesizer with -111dBc/Hz In-Band Phase Noise and an FOM of -242dB
Seyed Arash Mirhaj1, Yen-Cheng Kuan1, Huan-Neng Chen2, Chewn-Pu Jou2, Ming-Hsien Tsai2, Fu-Lung Hsueh2, Mau-Chung Frank Chang1 University of California, Los Angeles, CA, 2TSMC, Hsinchu, Taiwan 1 The noise performance of
ISSCC 2015
Session 15
Data Converters
An 85dB-DR 74.6dB-SNDR 50MHz-BW CT MASH ΔΣ Modulator in 28nm CMOS
MediaTek, Woburn, MA 1 2 A multi-stage noise-shaping (MASH) architecture is an attractive approach for its aggressive noise-shaping capability and relaxed stability requirements. However, in practice the quantization noi
ISSCC 2015
Session 15
Data Converters
A 4.5mW CT Self-Coupled ΔΣ Modulator with 2.2MHz BW and 90.4dB SNDR Using Residual ELD Compensation
front-end filter design for wireless communication applications. To achieve high resolution (DR>90dB) and low power dissipation (FoMs>170dB), architecture selection and circuit techniques are the main design issues. In [
ISSCC 2015
Session 15
Data Converters
A 115dB-DR Audio DAC with –61dBFS Out-of-Band Noise
Delectronics, Enschede, The Netherlands, 3 Teledyne DALSA Semiconductors, Enschede, The Netherlands 1 2 Out-of-band noise (OBN) is troublesome in analog circuits that process the output of a noise-shaping audio DAC. It c
ISSCC 2015
Session 15
Data Converters
A 0.8V 10b 80kS/s SAR ADC with Duty-Cycled Reference Generation
sensed signal. State-of-art SAR ADCs can accomplish this goal with high power-efficiency (<10fJ/conversion-step) [1-4]. The reference voltage design is critical for the ADC performance to obtain good PSRR, low line-sensi
ISSCC 2015
Session 15
Data Converters
A 0.6V 1.17ps PVT-Tolerant and Synthesizable Time-to-Digital Converter Using Stochastic Phase Interpolation with 16× Spatial Redundancy in 14nm FinFET Technology
timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of qu
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