Analog CMOS from 5 Micrometer to 5 Nanometer Willy Sansen

📋 论文概要

本文回顾了从5微米到5纳米工艺的模拟CMOS技术发展历程，重点讨论了物联网和智能手机等低功耗应用对模拟电路设计的挑战与演进。

💡 主要创新点

• 系统梳理了模拟CMOS技术从5微米到5纳米的关键技术节点和设计方法演变
• 强调了低功耗设计在物联网和移动设备中的核心地位，并分析了工艺缩放对模拟性能的影响

🏷 关键词

📄 原文摘要

The most important application of ICs, today, is most probably the Internet-ofThings. It involves sensor nodes and communications at the lowest-possible power levels. Similar low power levels are required for the next-generation smart-phones as images and video become increasing requirements, in phone, body-worn, and automotive applications. Whatever technology is used, portability requires reduced power consumption. Analog CMOS in 5 Micrometer technologies dates from the seventies as shown by Moore’s Law (Figure 1.3.1). In early chips, Analog circuits were dominant; as time progressed, digital became more prevalent, such that at 5 Nanometer it will overwhelm. Yet, Analog circuits traditionally establish the interface to Digital. Thus, they must be realized in mainstream digital technologies, and correspondingly, are forced to conform to evolving Digital. Note that in Figure 1.3.1, the projections to 10nm and 5nm in 2016 and 2020,

👥 作者与机构

Professor Emeritus, Katholieke Universiteit Leuven, Leuven, Belgium, 1.0 Introduction