A 10Gb/s Hybrid ADC-Based Receiver with Embedded 3-Tap Analog FFE and Dynamically-Enabled Digital Equalization in 65nm CMOS

📋 论文概要

本文提出了一种10Gb/s混合ADC接收器，集成了3抽头模拟前馈均衡器（FFE）和动态使能的数字均衡器（DFE），解决了高速串行链路中的符号间干扰问题。通过32路时间交织架构和循环展开技术，实现了312.5MHz时钟下的10Gb/s操作。

💡 主要创新点

• 提出混合ADC接收器架构，将模拟FFE与数字DFE结合，支持从全前光标到全后光标均衡抽头的动态组合控制。
• 采用循环展开架构和流水线寄存器组，满足数字3抽头DFE的关键反馈时序路径，实现全合成数字均衡器。
• 利用32路时间交织并行实现，每路时钟312.5MHz，在65nm CMOS工艺下达到10Gb/s速率。

🏷 关键词

📄 原文摘要

Sebastian Hoyos, Samuel Palermo control that allows all combinations ranging from all pre-cursor to all postcursor equalization taps. A loop-unrolled architecture is utilized to meet the critical feedback timing paths of the digital 3-tap DFE [6], with a pipeline register bank inserted to improve the timing slack before the DFE selection multiplexers. The digital equalizer is fully synthesized using a digital standard-cell library and auto-placed-and-routed. To enable 10Gb/s operation, we use a 32-way time-interleaved parallel implementation where each slice is clocked at 312.5MHz. Texas A&M University, College Station, TX ADC-based receivers are currently being proposed in high-speed serial link applications to enable flexible, complex, and robust digital equalization in order to support operation over high loss channels [1-3]. However, the power dissipation of the ADC, as well as the digital equalization that follows, is a major

👥 作者与机构

Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Keytaek Lee,