1GB/s 2Tb NAND Flash Multi-Chip Package with Frequency-Boosting Interface Chip and low-to-high hysteresis by implementing MN4 and MN3, respectively, to block the extra toggle.

📋 论文概要

该论文提出了一种基于频率提升接口芯片（F-Chip）和低到高迟滞技术的1GB/s 2Tb NAND闪存多芯片封装方案。通过实现ZQ校准和片上终端（ODT）改善了信号完整性，解决了高容量NAND闪存封装中的接口速度和信号质量问题。

💡 主要创新点

• 采用频率提升接口芯片（F-Chip）提高多芯片封装中NAND闪存的数据传输速率至1GB/s。
• 引入低到高迟滞技术，结合ZQ校准和ODT，增强信号完整性并降低功耗。

🏷 关键词

📄 原文摘要

Joon-Ho Shin, Chae-Hoon Kim, Seung-Woo Yu, Ji-Yeon Shin, Seon-Kyoo Lee, Devraj Rajagopal, Sang-Tae Kim, Kyeong-Tae Kang, Jeong-Joon Park, Yong-Jin Kwon, Min-Jae Lee, Sung-Hoon Kim, Seung-Hoon Shin, Hyung-Gon Kim, Jin-Tae Kim, Ki-Sung Kim, Han-Sung Joo, Chan-Jin Park, Jae-Hwan Kim, Man-Joong Lee, Do-Kook Kim, Hyang-Ja Yang, Dae-Seok Byeon, Ki-Tae Park, Kye-hyun Kyung, Jeong-Hyuk Choi Figure 7.6.3 presents a method of calibrating NAND driver strengths (DS) by utilizing ZQ calibration and on-die termination (ODT) implemented in the F-Chip. ZQ calibration has broadly used for better signal integrity over process, voltage and temperature (PVT) variations. On the other hand, external reference resistors for ZQ calibration on each NAND device cannot be easily equipped due to constraints on PCB space and package balls. In order to eliminate the constraints, the F-Chip trims all the NAND DS using the calibrated F-Chip DS.

👥 作者与机构

Hyun-Jin Kim, Jeong-Don Lim, Jang-Woo Lee, Dae-Hoon Na,