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ISSCC 2015Session 5 · ANALOG TECHNIQUESAnalog Circuits0.13µm CMOS

A 0.13µm Fully Digital Low-Dropout Regulator with Adaptive Control and Reduced Dynamic Stability for Ultra-Wide Dynamic Range

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📋 论文概要

该论文提出了一种采用0.13µm工艺的全数字低压差稳压器,通过自适应控制和降低动态稳定性技术,实现了超宽动态范围内的电压调节。解决了传统LDO在宽负载电流范围下效率低、稳定性差的问题。

💡 主要创新点

工艺节点
0.13µm CMOS
重要性
发表年份
ISSCC 2015

🏷 关键词

全数字低压差稳压器自适应控制动态稳定性

📄 原文摘要

An increasing number of power domains and of power states per domain, as well as decreasing decoupling capacitance per local grid and ultra-wide current dynamic range of digital load circuits (for low power on one end while maintaining performance at another) necessitate the design of high-efficiency, compact on-die voltage regulators providing ultra-fine grained spatio-temporal voltage distribution [1,2]. Digitally implementable linear regulators operated in low-dropout (LDO) mode, based on continuous time or discrete time control, exhibit process and voltage scalability [3-5], thus supplementing their analog counterparts [6]. This paper presents a discrete-time, fully digital, scan-programmable LDO macro in 0.13μm technology featuring greater than 90% current efficiency across a 50× current range, and 8× improvement in transient response time in response to large load steps. The baseline design (Fig. 5.6.1) features a 128b

👥 作者与机构

Saad Bin Nasir, Samantak Gangopadhyay, Arijit Raychowdhury

Georgia Institute of Technology, Atlanta, GA

分类:Analog Circuits · 年份:ISSCC 2015