A 16nm Auto-Calibrating Dynamically Adaptive Clock Distribution for Maximizing Supply-Voltage-Droop Tolerance Across a Wide Operating Range

📋 论文概要

该论文提出一种16nm工艺下的自动校准动态自适应时钟分布技术，用于最大化电源电压降容限。通过片上监测和自适应时钟频率调整，有效应对电源电压波动带来的性能与能效下降问题。

💡 主要创新点

• 提出自动校准机制，无需复杂模拟电路即可自适应调整时钟频率以应对电源电压降。
• 动态自适应时钟分布架构，能够在宽频率范围内快速响应电压变化，提升系统鲁棒性。

🏷 关键词

📄 原文摘要

supply voltage (VDD) droops when the current in the power delivery network abruptly changes in response to workload variations, thus degrading performance and energy efficiency. Previous adaptive circuit techniques aim to reduce the effects of VDD droops by sensing the VDD variation with an on-die monitor and adjusting the clock frequency (FCLK) [1-2] or by directly modulating the phase-locked loop (PLL) clock output with changes in the core VDD to implicitly adapt FCLK [3]. The adaptive response time and complex analog circuits limit the benefits of these techniques for a wide range of FCLK and VDD operating conditions. The adaptive clock distribution (ACD) [4-5] exploits the path clock-data delay compensation during a VDD droop to enable a sufficient response time to proactively adapt FCLK.

👥 作者与机构

Keith Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling,

Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine Qualcomm, Raleigh, NC System-on-chip (SoC) processor cores experience high-frequency