A 4-to-11GHz Injection-Locked Quarter-Rate Clocking for an Adaptive 153fJ/b Optical Receiver in 28nm FDSOI CMOS

📋 论文概要

本文提出一种4-11GHz注入锁定四分之一速率时钟方案，用于自适应光学接收机，在28nm FDSOI工艺中实现153fJ/b的能效，解决了注入锁定振荡器锁定范围窄的问题。

💡 主要创新点

• 设计具有宽锁定范围（4-11GHz）的环形注入锁定振荡器，适用于宽带应用。
• 利用注入锁定振荡器直接产生四分之一速率正交时钟，无需分频器，降低功耗和面积。
• 集成于低功耗自适应光学接收机，实现153fJ/b的能效目标。

🏷 关键词

📄 原文摘要

Modern SoC systems impose stringent requirements on on-chip clock generation and distribution. Ring-oscillator (RO) based injection-locked (IL) clocking has been used in the past [1] to provide a low-power, low-area and low-jitter solution. Ring-based injection-locked oscillators (ILO) can also be used to generate quadrature phases from a reference clock [2] without frequency division, which is desirable for half-rate and quarter-rate CDR. However, ILO inherently has a small locking range [3] making it less suitable for wideband applications. In addition, drift in the free-running frequency due to PVT variations may lead to poor jitter performance and locking failures [4]. Adding a PLL to an ILO provides frequency tracking. However, PLL-aided techniques have second-order characteristics that lead to jitter peaking. They also add design complexity and power consumption [5]. We present a frequency-tracking

👥 作者与机构

Mayank Raj, Saman Saeedi, Azita Emami

California Institute of Technology, Pasadena, CA