A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC Utilizing a Redundancy-Facilitated Background Error-Detection-and-Correction Scheme

📋 论文概要

该论文提出了一种利用冗余辅助背景误差检测与校正方案的13位SAR ADC，在6.4MS/s采样率下实现了5.5fJ/conv-step的能效，解决了高精度SAR ADC中DAC匹配限制和校准功耗高的问题。

💡 主要创新点

• 提出冗余辅助背景误差检测与校正方案，无需额外校准周期即可在线校正电容失配和比较器偏移。
• 通过冗余位设计简化误差检测逻辑，降低数字校准功耗，实现极低能效。

🏷 关键词

📄 原文摘要

g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental

👥 作者与机构

Ming Ding1, Pieter Harpe2, Yao-Hong Liu1, Benjamin Busze1,

Kathleen Philips1, Harmke de Groot1 Holst Centre / imec, Eindhoven, The Netherlands, Eindhoven University of Technology, Eindhoven, The Netherlands 1 2 Wireless standards, e