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本文实现了一款28nm CMOS工艺的4K H.265/HEVC视频编解码芯片，核心面积仅2.16mm²，能效达到0.5nJ/Pixel。该芯片集成了H.265和H.264双标准编解码器，适用于多格式智能手机应用，解决了超高清视频实时编解码的高功耗和面积挑战。
Han-Liang Chou, Chih-Ming Wang, Tung-Hsing Wu, Hue-Min Lin, Yi-Hsin Huang, Chia-Yun Cheng, Ting-An Lin, Chun-Chia Chen, Yu-Kun Lin, Min-Hao Chiu, Wei-Cing Li, Sheng-Jen Wang, Yen-Chieh Lai, Ping Chao, Chih-Da Chien, Meng-Jye Hu, Peng-Hao Wang, Fu-Chun Yeh, Yen-Chao Huang, Shun-Hsiang Chuang, Lien-Fei Chen, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Ryan Chen, HY Hsu, Kevin Jou MediaTek, Hsinchu, Taiwan A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm2. This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4) decoders into a single chip. It contains 3,558K logic gates and 308KB of internal SRAM. Moreover, it simplifies intra/inter-ratedistortion optimization (RDO) processes and reduces external bandwidth via line-store SRAM pool (LSSP) and data-bus translation (DBT) techniques. For
Chi-Cheng Ju, Tsu-Ming Liu, Kun-Bin Lee, Yung-Chang Chang,