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ISSCC 2015Session 3 · ULTRA-HIGH-SPEED WIRELINE TRANSCEIVERS AND ENERGY-EFFICIENT LINKSWireline I/O14nm CMOS

A 16-to-40Gb/s Quarter-Rate NRZ/PAM4 Dual-Mode Transmitter in 14nm CMOS

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📋 论文概要

本文提出一款采用14nm CMOS工艺的16-40Gb/s四分之一速率NRZ/PAM4双模式发射机,解决了高速SerDes中需要同时支持多种调制格式和宽频率范围的问题,避免了开发多个IP。

💡 主要创新点

工艺节点
14nm CMOS
重要性
发表年份
ISSCC 2015

🏷 关键词

NRZPAM4双模式发射机14nm CMOS高速SerDes

📄 原文摘要

to data-rates of 40Gb/s and beyond. Most previous standards for these networking applications use NRZ signaling. However, practical signal integrity constraints have led to a renewed interest in also supporting PAM4 for some applications and loss profiles [1-2]. Recently, several transmitters have been reported that operate between 28 and 60Gb/s using NRZ or PAM4 modulation exclusively [2-4]. However, high-speed SerDes building blocks that support both a wide frequency range and multiple forms of modulation provide more compatibility between components and avoid the development of multiple IPs. In addition, these blocks must continue to scale into the next-generation of CMOS process technologies to lower the cost by reducing area and power consumption. This paper presents a dual-mode transmitter (TX) implemented in 14nm CMOS that

👥 作者与机构

Jihwan Kim, Ajay Balankutty, Amr Elshazly, Yan-Yu Huang, Hang Song,

Kai Yu, Frank O’Mahony Intel, Hillsboro, OR Emerging standards in wireline communication are defining a path

分类:Wireline I/O · 年份:ISSCC 2015