A 2.4mm2 130mW MMSE-Nonbinary-LDPC Iterative Detector-Decoder for 4×4 256-QAM MIMO in 65nm CMOS

📋 论文概要

该论文提出了一种用于4×4 256-QAM MIMO系统的MMSE-非二进制LDPC迭代检测-解码器，在65nm CMOS工艺下实现了2.4mm²面积和130mW功耗，通过软输入软输出检测与解码的迭代交换软信息，降低了可靠传输所需的信噪比。

💡 主要创新点

• 采用MMSE检测与非二进制LDPC解码的迭代结构，提升了MIMO系统的检测与解码性能。
• 在65nm CMOS工艺下实现了低面积（2.4mm²）和低功耗（130mW）的硬件实现，适用于移动通信场景。

🏷 关键词

📄 原文摘要

The latest multiple-input multiple-output (MIMO) wireless systems have adopted iterative detection and decoding (IDD) to reduce the signal-to-noise ratio (SNR) required for a reliable transmission. An IDD system consists of a soft-in soft-out (SISO) detector to cancel interference, and a SISO forward-error correction (FEC) decoder to remove errors. The two blocks exchange soft information to improve the SNR iteratively. State-of-the-art IDDs based on sphere decoding (SD) and low-density parity-check (LDPC) FEC have been demonstrated in [1],

👥 作者与机构

Chia-Hsiang Chen, Wei Tang, Zhengya Zhang

University of Michigan, Ann Arbor, MI