A 5.5mW 6b 5GS/s 4×-Interleaved 3b/cycle SAR ADC in 65nm CMOS

📋 论文概要

该论文提出了一种在65nm CMOS工艺下实现的6位5GS/s 4倍交织3位/周期SAR ADC，功耗仅为5.5mW。通过多比特处理和交织并行方案，解决了高速下晶体管尺寸缩放导致寄生效应增加和能效下降的问题。

💡 主要创新点

• 采用3位/周期的SAR转换架构，在单个周期内完成3位量化，显著提高了转换速率。
• 通过4倍交织技术，进一步将有效采样率提升至5GS/s，同时保持低功耗。
• 优化了电路设计以降低寄生效应影响，实现了高能效的GHz级采样ADC。

🏷 关键词

📄 原文摘要

Seng-Pan U1,2, R. P. Martins1,3 University of Macau, Macao, China, Synopsys, Macao, China, 3 Instituto Superior Tecnico, Universidade de Lisboa, Portugal 1 2 Communication devices such as 60GHz-band receivers and serial links demand power-efficient low-resolution gigahertz-sampling-rate ADCs. However, the energy efficiency of ADCs is degraded by scaling up transistor widths in the building blocks for high speed, thus increasing the impact of intrinsic parasitics. Parallel schemes like multi-bit processing and interleaving [1], can ease the problems caused by scaling and lead to better efficiency if the hardware overhead is wisely reduced [2]. This paper presents a combination of 4× time interleaving and 3b/cycle multi-bit SAR ADC in 65nm CMOS, achieving a Nyquist FoM of 39fJ/conv-step for 5GS/s at 1V supply. Figure 26.5.1 shows the block diagram of the ADC, which consists of four interleaved channels. The differential input signals are first sampled onto the top

👥 作者与机构

Chi-Hang Chan1, Yan Zhu1, Sai-Weng Sin1,