A 13.1-to-28GHz Fractional-N PLL in 32nm SOI CMOS with a ΔΣ Noise-Cancellation Scheme

📋 论文概要

该论文提出了一种在32nm SOI CMOS工艺中实现的13.1至28GHz分数-N锁相环（PLL），通过引入ΔΣ噪声消除方案来抑制分数-N合成中的确定性噪声分量，从而在宽调谐范围内生成干净的时钟信号，适用于可重构无线电和雷达等噪声敏感应用。

💡 主要创新点

• 提出了宽调谐范围（13.1-28GHz）的分数-N PLL架构，覆盖多个频段。
• 设计了ΔΣ噪声消除方案，有效降低分数-N PLL中的确定性相位噪声。

🏷 关键词

📄 原文摘要

as in reconfigurable radio and radar applications, is the generation of a clean clock signal supporting a wide range of frequencies. The introduction of fractional-N synthesis capability for wide-tuning-range applications enables generation of arbitrary output frequencies within that range from a single choice of reference frequency. A critical challenge in fractional-N synthesizer design is the cancellation of the deterministic component of the fractional-N ΔΣ noise, allowing fractional-N solutions to be applied even in noise-sensitive contexts. In this work, we present a flexible, wide tuning range, fractional-N PLL implemented in 32nm SOI CMOS technology, introducing two separate methods—one in the proportional path and one in the integral path—to process and suppress ΔΣ noise. The

👥 作者与机构

Mark Ferriss, Bodhisatwa Sadhu, Alexander Rylyakov,

Herschel Ainspan, Daniel Friedman IBM Research, Yorktown Heights, NY A key challenge in high-performance I/O, as well