A 0.009mm2 2.06mW 32-to-2000MHz 2nd-Order ΔΣ Analogous Bang-Bang Digital PLL with Feed-Forward Delay-Locked and Phase-Locked Operations in 14nm FinFET Technology

📋 论文概要

本文提出了一种面积为0.009mm²、功耗2.06mW、频率范围32-2000MHz的二阶ΔΣ模拟bang-bang数字锁相环（PLL），通过前馈延迟锁定和相位环路实现宽频率范围和低功耗。该设计针对先进工艺下模拟PLL面临的挑战，采用全数字方式替代传统模拟PLL。

💡 主要创新点

• 采用二阶ΔΣ模拟bang-bang架构，在数字PLL中实现类似模拟的噪声整形，同时保持数字电路的抗干扰性和可扩展性。
• 引入前馈延迟锁定和相位环路，有效扩展了工作频率范围（32-2000MHz），且面积和功耗极低。

🏷 关键词

📄 原文摘要

architectures, from a planar structure to a FinFET to achieve decreased leakage, further downscaling, and better sub-threshold slope, even under a lower power supply [1]. Downscaling trends have forced the analog semiconductor industry to move to the digital domain to maintain functionality in light of increasing short-channel effects and device mismatch. Furthermore, the main goal of the new technology is to achieve faster speed and lower cost. In leading-edge processes and design environments, conventional analog PLLs in systems-on-chip (SoCs) are being replaced by digitally operated PLLs to meet clock requirements for optimal overall system performance. While a widely used time-to-digital converter (TDC)-based digital PLL (TDC-DPLL) has a linear loop

👥 作者与机构

Minyoung Song, Taeik Kim, Jihyun Kim, Wooseok Kim,

Sung-Jin Kim, Hojin Park Samsung Electronics, Hwaseong, Korea The race to deep sub-micron CMOS technology has resulted in a change in device