A 70.5-to-85.5GHz 65nm Phase-Locked Loop with Passive Scaling of Loop Filter

📋 论文概要

本文提出了一种采用被动缩放环路滤波器的65nm CMOS锁相环，工作频率范围为70.5至85.5GHz，有效解决了传统主动环路滤波器引入额外噪声的问题，实现了全集成且低相位噪声的毫米波频率合成器。

💡 主要创新点

• 采用被动缩放技术替代主动环路滤波器，无需运算放大器，避免了主动噪声引入，同时实现了环路滤波器电容的片上集成。
• 在65nm CMOS工艺上实现了70.5-85.5GHz的宽频率调谐范围，适用于71-86GHz频段的应用需求。

🏷 关键词

📄 原文摘要

(PLLs) are required to have wide a frequency tuning range from 71 to 86GHz and low phase noise of -90dBc/Hz @1MHz [1], which are still very challenging even with aggressive CMOS scaling [2]. Another issue associated with PLLs is the difficulty to integrate on-chip loop filters. Active loop filters are employed to scale down the loop filter capacitors and enable them to be fully integrated on-chip [3]. However, this method suffers from large active noise induced by the op-amp. Moreover, as the capacitance is reduced, the resistor value has to be increased to maintain the same zero frequency, leading to higher thermal noise and limiting achievable scaling factor. Another method is to integrate digital loop filters in all-digital PLLs (ADPLLs) [4]. Unfortunately, the quantization noise of

👥 作者与机构

Zhiqiang Huang1, Howard Cam Luong1, Baoyong Chi2, Zhihua Wang2, Haikun Jia2

Hong Kong University of Science and Technology, Hong Kong, China, Tsinghua University, Beijing, China 1 2 To support 16-QAM modulation in E-band applications, phase-locked loops