A 24-to-35Gb/s ×4 VCSEL Driver IC with Multi-Rate Referenceless CDR in 0.13μm SiGe BiCMOS

📋 论文概要

本文提出了一款24-35Gb/s四通道VCSEL驱动芯片，集成了多速率无参考时钟的时钟数据恢复电路。该芯片采用双环混合CDR结构，实现了宽调谐范围的多速率操作，解决了高密度光互连中多VCO占用面积大的问题。

💡 主要创新点

• 采用双环混合CDR架构，实现多速率操作且无需参考时钟
• 通过共享VCO或优化VCO布局，减小面积以支持高密度光互连
• 在0.13μm SiGe BiCMOS工艺上实现了24-35Gb/s的宽数据率范围

🏷 关键词

📄 原文摘要

and high-density interconnects because of the high-bandwidth and low-crosstalk properties of optical signals. The next challenge for optical interconnects is to move to a serial data-rate of 25Gb/s or higher [1,2]. To achieve flexible interconnects on a bandwidth demand, a CDR is required to operate at multiple rates in a wide tuning range. A selectable multi-VCO structure is one method to overcome this issue. However, when multi-VCOs are allocated in each channel, the large size of VCOs makes it difficult to achieve a high-density optical link. In this paper, we present a dual-loop hybrid CDR including a phase interpolator (PI) loop for phase tracking and a common VCO loop situated outside the channel areas for frequency acquisition. We develop a quadrant-switching analog PI-loop

👥 作者与机构

Yukito Tsunoda, Takayuki Shibasaki, Satoshi Ide, Toshihiko Mori,

Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura Fujitsu Laboratories, Kawasaki, Japan The optical interconnect technologies are a promising solution for high-speed