A 5.9pJ/b 10Gb/s Serial Link with Unequalized MM-CDR in 14nm Tri-Gate CMOS

📋 论文概要

该论文提出了一种采用不等化MM-CDR的2.5-10Gb/s串行链路，在14nm三栅极CMOS工艺中实现，解决了在先进逻辑工艺中实现模拟功能的挑战，并实现了5.9pJ/b的高能效。

💡 主要创新点

• 采用不等化Muller-Mueller CDR（MM-CDR）技术，无需均衡器即可实现数据恢复，降低了功耗和设计复杂度。
• 在14nm tri-gate CMOS逻辑优化工艺中成功实现了高性能模拟电路，克服了传统模拟设计在先进工艺中的困难。
• 支持2.5-10Gb/s宽范围数据速率，并保持链路鲁棒性，适用于多种信道特性。

🏷 关键词

📄 原文摘要

links integrated in advanced CMOS are ubiquitous in modern microprocessor systems. These commodity links have fixed performance specs and therefore realize the benefit of technology scaling in area and power reduction at high data rates. To realize significant scaling benefits, these designs must overcome the challenges associated with implementing analog functions in scaled logic-optimized processes while maintaining link robustness over a wide range of channel characteristics and third party components. This work describes a 2.5-to-10 Gb/s serial link implemented in 14nm tri-gate CMOS using logic-pitch transistors exclusively. The half-rate embedded-clock transceiver architecture (Fig. 10.5.1) [1] consists of a 3-tap current-mode (CM)

👥 作者与机构

Rajeev Dokania1, Alexandra Kern1, Mike He2, Adam Faust1,

Richard Tseng1, Skyler Weaver1, Kai Yu1, Christiaan Bil3, Tao Liang3, Frank O’Mahony1 Intel, Hillsboro, OR, 2Intel, Santa Clara, CA, 3Intel, Hudson, MA 1 High-speed serial