Enabling Wide Autonomous DVFS in a 22nm Graphics Execution Core Using a Digitally Controlled Hybrid LDO/Switched-Capacitor VR with Fast Droop Mitigation

📋 论文概要

该论文提出了一种在22nm工艺下用于图形执行核心的宽范围自主动态电压频率调整（DVFS）技术，通过数字控制的混合低压差稳压器/开关电容转换器实现。解决了在共享电源轨下不同模块电压需求不同导致的能量浪费问题，并支持从近阈值电压到涡轮增压区域的宽范围高效运行。

💡 主要创新点

• 提出了一种数字控制的混合LDO/开关电容转换器架构，实现了宽范围自主DVFS。
• 在近阈值电压区域采用电路辅助技术降低固有最小电压，在涡轮区域采用自适应时钟减少电压骤降保护带。

🏷 关键词

📄 原文摘要

Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De Intel, Hillsboro, OR A graphics execution core in 22nm improves energy efficiency across a wide DVFS range, from the near-threshold voltage (NTV) region, where circuit assist lowers intrinsic VMIN, to the turbo region, where adaptive clocking reduces the voltage-droop guard-band [1]. When powered with a shared rail, however, energy is wasted in the core if other blocks demand higher voltage and performance. Alternately, a per-core fully-integrated voltage regulator (VR) provides a cost-effective means to realize autonomous DVFS [2-4]. In this paper, we present a graphics core that is supplied by a fully integrated and digitally controlled hybrid low-drop-out (LDO)/switched-capacitor voltage regulator (SCVR) with fast droop response (Fig. 8.6.1). While the LDO VR

👥 作者与机构

Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain,