KAIST, Daejeon, Korea, 3 Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea 1 2 Low-power CMOS reference clock oscillators have been widely used in miniaturized SoCs for emerging microsystems such as implantable biomedical devices and smart sensors [1-3]. In such SoCs, as the supply voltage shrinks and the level of analog and digital circuit integration increases to meet rigorous power and area constraints, the noise from other blocks (especially digital blocks) couples through supply and ground lines and poses a serious threat to the performance of CMOS reference clock oscillators. Although relaxation oscillators can provide high frequency stability as well as low noise [1-3], they have poor tolerance to supply and ground noise due to supply-sensitive building blocks such as reference voltage generators and single-ended comparators. One way of making them immune to the supply noise
Junghyup Lee1, Pyoungwon Park1, SeongHwan Cho2, Minkyu Je3
Institute of Microelectronics, Singapore, Singapore,