← 返回论文列表 📄 下载原文 PDF  ISSCC 2015 · 8.7
ISSCC 2015Session 8 · LOW-POWER DIGITAL TECHNIQUESDigital Circuits

Dual-Use Low-Drop-Out Regulator / Power Gate with Linear and On-Off Conduction Modes for Microprocessor On-Die Supply Voltages in 14nm

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

该论文提出了一种双用低压差稳压器/电源门控电路,具有线性和开关导通模式,用于微处理器片上供电。它解决了多核处理器中不同单元需要不同供电电压且平台面积减小的挑战。

💡 主要创新点

重要性
发表年份
ISSCC 2015

🏷 关键词

低压差稳压器电源门控微处理器

📄 原文摘要

In recent generations of microprocessors, there has been an increase in the number and types of processors integrated on the same die. For example, in [1] several IA (Intel architecture) cores have been integrated on-chip with a graphics processor. Multi-core trends are expected to increase in future generations with different cores and units requiring varying supply voltages. As platform footprints are also required to decrease, this causes a unique challenge for voltage regulation. In [2], an on-die switching fully integrated voltage regulator (FIVR) was demonstrated, which presents a very good solution in many cases. However, the FIVR requires inductors, which may not always be available. In addition, it may be desirable to sub-divide some of the FIVR domains using power gates and/or linear voltage regulators, such as low-drop-out regulators (LDO). LDOs can be used to enable different units of the chip to operate at their

👥 作者与机构

Kosta Luria, Joseph Shor, Michael Zelikson, Alex Lyakhov

Intel, Yakum, Israel

分类:Digital Circuits · 年份:ISSCC 2015