A 21fJ/conv-step 9 ENOB 1.6GS/s 2× Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS

📋 论文概要

该论文提出了一种2路时间交织的FATI SAR ADC，通过前端Flash ADC提供多比特MSB来提升子通道SAR ADC的转换速度，从而减少时间交织通道数。同时，论文实现了背景偏移和时序歪斜校准，利用SAR ADC代码中嵌入的时序信息进行校准，解决了时间交织架构中的通道匹配问题。

💡 主要创新点

• 采用Flash辅助时间交织（FATI）SAR结构，前端Flash ADC提供多比特MSB，显著提升子通道SAR ADC的转换速度，从而减少所需的时间交织通道数，降低电路复杂度。
• 提出背景偏移和时序歪斜校准技术，利用每个SAR ADC的代码中嵌入的时序歪斜信息进行校准，无需额外参考信号，实现低功耗、高精度的通道匹配。

🏷 关键词

📄 原文摘要

taken advantage of timeinterleaved (TI) architectures with low-power SAR ADCs for their sub-channels. However, given that the TI architecture needs to satisfy matching requirements between channels, the circuit complexity arising from the calibrations has often become a considerable burden. In order to reduce the number of channels in TI SAR ADCs, a flash-assisted TI (FATI) SAR structure [1] can be utilized to enhance the conversion speed of a sub-channel SAR ADC due to the multi-bit MSBs from a front-end flash ADC. In addition, because the codes from each SAR ADC embed the timing skew information of the corresponding channel, the structure can extract timing skew information in an efficient manner [2]. Despite these advantages of FATI SAR ADCs, as the required conversion rate increases,

👥 作者与机构

Ba-Ro-Saim Sung1, Dong-Shin Jo1, Il-Hoon Jang1, Dong-Suk Lee2,

Yong-Sang You2, Yong-Hee Lee2, Ho-Jin Park2, Seung-Tak Ryu1 KAIST, Daejeon, Korea, 2Samsung Electronics, Hwaseong, Korea 1 Recently reported high-speed ADCs have mostly