A 14b 35MS/s SAR ADC Achieving 75dB SNDR and 99dB SFDR with Loop-Embedded Input Buffer in 40nm CMOS

📋 论文概要

本文提出了一款14位35MS/s的逐次逼近寄存器型模数转换器（SAR ADC），采用40nm CMOS工艺，通过环路嵌入式输入缓冲器技术实现了75dB SNDR和99dB SFDR。该设计解决了高分辨率SAR ADC中输入缓冲器线性度不足的问题，在保持低延迟的同时达到了高性能。

💡 主要创新点

• 提出环路嵌入式输入缓冲器（loop-embedded input buffer），将缓冲器嵌入SAR环路中，有效提高了线性度和驱动能力。
• 在40nm CMOS工艺下实现了14位分辨率、35MS/s采样率，同时达到75dB SNDR和99dB SFDR，优于传统流水线和ΔΣ架构的功耗效率。

🏷 关键词

📄 原文摘要

NXP Semiconductors, Eindhoven, The Netherlands 1 2 Successive-approximation-register (SAR) analog-to-digital converters (ADCs) have generated a great deal of interest in the past several years. While most of the recent work focuses on low-to-moderate resolution designs (8 to 10b), we are now also seeing significant advancements in the high-resolution space, targeting ≥14b at 10 to 100MS/s [1,2]. Traditionally, this range has been dominated by pipelined and ΔΣ architectures. However, several applications in instrumentation, high-speed control, and interference cancellation require low latency, making the SAR topology attractive. While the SAR ADCs of [1,2,3] demonstrate efficient digitization at high speed and resolution, the challenge of driving a large sampling capacitor (CS) with high accuracy in a short sampling window (10 to 20% of the cycle or a few nanoseconds) is often not addressed. One way to ease the driving requirement

👥 作者与机构

Martin Krämer1, Erwin Janssen2, Kostas Doris2, Boris Murmann1

Stanford University, Stanford, CA,