A 0.45-to-0.7V 1-to-6Gb/s 0.29-to-0.58pJ/b Source-Synchronous Transceiver Using Automatic Phase Calibration in 65nm CMOS

📋 论文概要

本文提出了一种采用自动相位校准的源同步收发器，在65nm CMOS工艺下实现了0.45-0.7V的低电压供电和1-6Gb/s的数据率。该设计通过自动相位校准技术克服了低电压下多相时钟生成对器件失配的敏感性，从而在宽电压范围内达到0.29-0.58pJ/b的高能效。

💡 主要创新点

• 提出自动相位校准技术，能够自动补偿低电压下多相时钟的相位失配，确保收发器正常工作。
• 采用源同步架构，结合低电压和并行化设计，在宽电压范围内实现宽数据率（1-6Gb/s）的高能效传输。

🏷 关键词

📄 原文摘要

greatly reduce power in serial link transceivers. Ideally, power efficiency at a given data rate can be improved by reducing VDD while increasing the number of multiplexed circuits operating in parallel at lower clock frequencies [1]. Though increasing the amount of parallelism is desirable to scale VDD, in practice, it is limited by two main factors. First, increased sensitivity to device variations (threshold voltage/dimension mismatch) at lower VDD makes it extremely challenging to generate equally spaced multi-phase clocks needed in multiplexed transmitter and receiver. Phase calibration methods can correct phase-spacing errors [2,3], but their effectiveness at lower VDD is limited as the calibration circuits themselves

👥 作者与机构

Woo-Seok Choi1, Guanghua Shu1, Mrunmay Talegaonkar1, Yubo Liu1,

Da Wei1, Luca Benini2, Pavan Kumar Hanumolu1 University of Illinois, Urbana, IL, University of Bologna, Bologna, Italy 1 2 Supply voltage (VDD) scaling offers a means to