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ISSCC 2015Session 8 · LOW-POWER DIGITAL TECHNIQUESDigital Circuits28nm FDSOI

A 0.33V/-40°C Process/Temperature Closed-Loop Compensation SoC Embedding All-Digital Clock Multiplier and DC-DC Converter Exploiting FDSOI 28nm Back-Gate Biasing

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📋 论文概要

该论文提出了一款在28nm FDSOI工艺上设计的32位SoC,能够在0.33V超低电压和-40°C低温下工作,通过闭环补偿技术应对工艺和温度变化。芯片集成了全数字时钟倍频器和DC-DC转换器,支持能效模式(0.45V)和低泄漏模式(0.33V),解决了极低电压下电路性能与可靠性的挑战。

💡 主要创新点

工艺节点
28nm FDSOI
重要性
发表年份
ISSCC 2015

🏷 关键词

超低电压闭环补偿全数字时钟倍频器DC-DC转换器SoC

📄 原文摘要

Jean-Marc Daveau1, Cyril Bottoni1, David Bol4, Julien De-Vos4, Dominique Zamora5, Benjamin Coeffic1, Dimitri Soussan1, Damien Croain1, Mehdi Naceur6, Pierre Schamberger6, Philippe Roche1, Dennis Sylvester3 STMicroelectronics, Crolles, France, Aix-Marseille University, Marseille, France, 3 University of Michigan, Ann Arbor, MI, 4 Universite Catholique de Louvain, Louvain La Neuve, Belgium, 5 MAYA Technologies, Grenoble, France, 6 EASii-IC, Grenoble, France 1 2 A 32b SoC is designed in 28nm FDSOI to operate in either an energy-efficiency (EE) mode, at 0.45V, or low-leakage (LL) mode, at 0.33V, with processtemperature compensation. At near threshold, it overcomes low transistor current at negative temperatures, the need for an extra digital supply IO, and the clocking power costs faced by the internet-of-things (IoT) and wearable systems. The system includes: 1) an all-digital single-supply open-loop clock

👥 作者与机构

Sylvain Clerc1, Mehdi Saligane1,2,3, Fady Abouzeid1, Martin Cochet1,2,

分类:Digital Circuits · 年份:ISSCC 2015