A 6.75-to-8.25GHz 2.25mW 190fsrms Integrated-Jitter PVT-Insensitive Injection-Locked Clock Multiplier Using All-Digital Continuous Frequency-Tracking Loop in 65nm CMOS

📋 论文概要

该论文提出了一种全数字的PVT不敏感注入锁定时钟乘法器，工作频率为6.75-8.25GHz，功耗仅2.25mW，实现了190fsrms的集成抖动。通过全数字技术解决了传统注入锁定振荡器对工艺、电压和温度变化敏感的问题。

💡 主要创新点

• 提出全数字PVT不敏感技术，使注入锁定时钟乘法器能在宽PVT范围内保持低抖动性能
• 采用全数字架构替代传统模拟电路，降低了功耗并提高了集成度

🏷 关键词

📄 原文摘要

University of Illinois, Urbana, IL Sub-harmonically injection locked oscillators provide a simple means for generating very-low-noise high-frequency clocks in a power, and area efficient manner [1-5]. Ideally, a free-running oscillator can be locked to the Nth harmonic of a reference clock simply by injecting narrow pulses at reference frequency (FREF) into the oscillator, such that FOUT=NFREF. In the locked state, the oscillator tracks the reference clock and its close-in phase noise is greatly suppressed. As such, the phase noise of an injection-locked clock multiplier (ILCM) is limited only by the noise of reference clock. However, in practice, there are several design challenges that limit usage of ILCMs. First, lock-in range (ΔFL) of the injection-locked oscillator is limited. Therefore, separate frequency tuning, typically performed using a phase-locked loop (PLL) is needed to bring the

👥 作者与机构

Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu