A 2.2GHz -242dB-FOM 4.2mW ADC-PLL Using Digital Sub-Sampling Architecture

📋 论文概要

该论文提出了一种基于数字亚采样架构的ADC-PLL，利用电压域数字化实现低功耗低抖动频率合成。在65nm CMOS工艺中实现了2.2GHz振荡频率、4.2mW功耗和-242dB的FOM，解决了传统PLL功耗与噪声折中的问题。

💡 主要创新点

• 采用数字亚采样架构结合ADC进行电压域数字化，避免了传统电荷泵和模拟环路滤波器的功耗与面积开销。
• 使用18位Class-C数字控制振荡器（DCO）和4位比较器，结合数字环路滤波器（DLF）与频率锁定环（FLL），实现低抖动和快速锁定。

🏷 关键词

📄 原文摘要

loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequency-locked loop (FLL). Implemented in 65nm CMOS technology, the proposed PLL reaches an in-band phase noise of -112dBc/Hz and an RMS jitter of 380fs at 2.2GHz oscillation frequency. An FOM of -242dB has been achieved with a power consumption of only 4.2 mW. Figure 25.2.1 shows a conceptual diagram of the proposed ADC-based all-digital PLL (ADC-PLL), which is based on a voltage-domain digitization rather than a time-domain counterpart. TDCs or PFD/CPs in conventional PLLs are replaced by an ADC, which has advantages in terms of a finer resolution and lower power

👥 作者与机构

Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno,

Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, Japan This paper presents an all-digital phase-locked