A 1.22ps Integrated-Jitter 0.25-to-4GHz Fractional-N ADPLL in 16nm FinFET CMOS

📋 论文概要

该论文提出了一款在16nm FinFET CMOS工艺中实现的分数N全数字锁相环（ADPLL），工作频率范围为0.25至4GHz，集成抖动仅为1.22ps。利用FinFET器件作为数字开关，克服了其模拟线性特性差的限制，实现了高性能和快速锁定的PLL。

💡 主要创新点

• 首次在16nm FinFET工艺中实现全数字PLL，利用FinFET作为开关而非线性放大器，解决了FinFET器件尺寸有限不适用于传统模拟设计的问题。
• 实现了0.25至4GHz的宽频率范围和1.22ps的超低集成抖动，性能优于先前在平面工艺中的ADPLL。
• 采用分数N架构和数字校准技术，实现了快速锁定和良好的可移植性。

🏷 关键词

📄 原文摘要

(ADPLLs) offer faster locking time, easier portability and better performance in advanced semiconductor processes as compared to analog PLLs. Advanced FinFET devices exhibit better gm and ION than planar devices [1], but they are offered only in a limited number of device sizes, thus precluding their use in traditional analog design styles. In an ADPLL, the transistors are used as switches with little regard to their linear analog properties. Hence, ADPLL performance should improve with the adoption of FinFET devices. Inverter delay in a 16nm FinFET process is less than half of that in a 28nm planar process, improving in-band phase noise (PN) by around 6dB

👥 作者与机构

Tsung-Hsien Tsai1, Min-Shueh Yuan1, Chih-Hsien Chang1,

Chia-Chun Liao1, Chao-Chieh Li1, Robert Bogdan Staszewski2 TSMC, Hsinchu, Taiwan, Delft University of Technology, Delft, The Netherlands 1 2 All-digital phase-locked loops