A 36Gb/s PAM4 Transmitter Using an 8b 18GS/s DAC in 28nm CMOS

📋 论文概要

该论文提出了一种采用8位18GS/s DAC的36Gb/s PAM4发射机，解决了高速串行链路中信道、封装和芯片寄生效应带来的信号完整性问题。通过PAM4调制和高速DAC设计，实现了更高的数据传输速率。

💡 主要创新点

• 采用8位18GS/s DAC实现PAM4信号生成，支持36Gb/s数据速率。
• 针对高速链路中的阻抗不连续和寄生电容问题进行了优化设计。

🏷 关键词

📄 原文摘要

signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more severe and do not benefit from process scaling in the same fashion that circuit design does. Reflections from impedance discontinuities in the PCB and package caused by vias and connectors introduce significant signal loss and distortions at higher frequencies. Even with an ideal channel, at every package-die interface, there is an intrinsic parasitic capacitance due to the pads and the ESD circuit amounting to at least 150fF, and a 50Ω resistor termination at both the transmit and receive ends resulting in an intrinsic pole at 23GHz or lower. In light of all these limitations, serial NRZ signaling beyond 60Gb/s

👥 作者与机构

Ali Nazemi, Kangmin Hu, Burak Catli, Delong Cui, Ullas Singh, Tim He,

Zhi Huang, Bo Zhang, Afshin Momtaz, Jun Cao Broadcom, Irvine, CA At data rates beyond 10Gb/s, most wireline links employ NRZ