A 5GHz -95dBc-Reference-Spur 9.5mW Digital Fractional-N PLL Using Reference-Multiplied Time-to-Digital Converter and Reference-Spur Cancellation in 65nm CMOS

📋 论文概要

提出一种采用参考倍乘时间数字转换器的5GHz数字分数N锁相环，实现了-95dBc参考杂散和9.5mW功耗，解决了传统DPLL中量化噪声高和模块噪声要求严格的问题。

💡 主要创新点

• 采用参考倍乘架构，提高ΔΣ调制器过采样率，将量化噪声推向高频，无需复杂噪声消除。
• 通过降低分频值，放宽PLL构建模块的噪声要求，实现低功耗设计。

🏷 关键词

📄 原文摘要

proposed for a low-power, low-noise fractional-N frequency synthesizer. Among the various innovations, a reference-multiplied architecture offers distinct advantages compared to conventional DPLLs [1]. First, low quantization noise (q-noise) can be achieved without complex q-noise cancellation schemes, since the delta-sigma modulator (DSM) has a high oversampling ratio and its q-noise is pushed to higher frequencies. Second, noise requirements of PLL building blocks become less stringent as the division value is reduced. For a digital PLL using a Nyquist-rate time-to-digital converter (TDC), if the reference is multiplied by N the time resolution of the TDC can be reduced by √N for the same noise level. Unfortunately, one drawback of the reference-multiplied PLL is the

👥 作者与机构

Hyojun Kim1, Jinwoo Sang2, Hyunik Kim1, Youngwoo Jo1,

Taeik Kim2, Hojin Park2, SeongHwan Cho1 KAIST, Daejeon, Korea, Samsung Electronics, Hwaseong, Korea 1 2 Since the advent of digital PLLs (DPLLs), various techniques have been