A 3.3ns-Access-Time 71.2μW/MHz 1Mb Embedded STT-MRAM Using Physically Eliminated Read-Disturb Scheme and Normally-Off Memory Architecture

📋 论文概要

该论文提出了一种1Mb嵌入式STT-MRAM，采用物理消除读干扰方案和常关模式，实现了3.3ns的访问时间和71.2μW/MHz的功耗，解决了传统STT-MRAM在读操作中可能出现的干扰问题，并显著降低了功耗。

💡 主要创新点

• 提出物理消除读干扰方案，通过电路设计从根本上避免读操作对存储单元的干扰，提高可靠性。
• 采用常关模式（Normally-Off）降低待机功耗，实现低功耗嵌入式非易失性存储。
• 在1Mb容量下实现3.3ns高速访问，同时保持71.2μW/MHz的低功耗，适用于高速低功耗工作存储器。

🏷 关键词

📄 原文摘要

Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita Toshiba, Kawasaki, Japan Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility. Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1]. Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2]. Advanced perpendicular STT-MRAM achieve ~3× power saving by reducing leakage current in memory cells compared with SRAM for last level cache (LLC) [3]. Such high-speed RAM applications, however, entail several issues: the probability of read disturbance error increases and the active power of STT-MRAM must be decreased for higher access speed. Moreover, the leakage power of peripheral circuits must be

👥 作者与机构

Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe,