A 0.048mm2 3mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique

📋 论文概要

提出一种采用软注入锁定技术的全可综合分数-N PLL，面积仅0.048mm²，功耗3mW。解决了传统分数-N PLL需要时间数字转换器（TDC）而不利于数字综合流程的问题，实现了低功耗小面积的全数字设计。

💡 主要创新点

• 采用软注入锁定技术实现分数-N操作，避免使用TDC，使得PLL完全可综合，便于SoC集成。
• 在极小的芯片面积（0.048mm²）和低功耗（3mW）下实现了分数-N锁相环，适合嵌入式应用。

🏷 关键词

📄 原文摘要

Systems-onChip (SoCs), which contain microprocessors, I/O interfaces, memories, power management, and communication systems. Fully synthesizable PLLs [1-2], designed using a pure digital design flow, have been proposed to reduce the design cost and allow easier integration. To achieve high-frequency resolution, PLLs are required to operate in fractional-N mode, in addition to integer-N mode. There are several architectures available [5-6] for realizing fractional-N operation. However, the existing topologies are not well suited for synthesis, as they require a time-to-digital converter (TDC) [3] and a digital-to-time converter (DTC) [4-5]. TDCs and DTCs are vulnerable to layout uncertainty, arising from automatic place and route (P&R), introducing linearity degradation and leading

👥 作者与机构

Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan,

Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa Tokyo Institute of Technology, Tokyo, Japan Phase-locked loops (PLLs) are a crucial building block in modern