An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM Cortex-M0+ Subsystem in 65nm CMOS for WSN Applications

📋 论文概要

本文提出了一个用于无线传感器网络的亚阈值ARM Cortex-M0+子系统，在65nm CMOS工艺中实现了80nW的保持功耗和11.7pJ/周期的活跃功耗，解决了物联网节点能量效率与成本问题。

💡 主要创新点

• 完整亚阈值ARM Cortex-M0+微处理器子系统的设计与实现，兼顾超低功耗与性能。
• 创新的保留技术，使保持功耗低至80nW，同时活跃功耗仅11.7pJ/周期。
• 针对无线传感器网络应用，在低成本65nm工艺中实现了高能效集成。

🏷 关键词

📄 原文摘要

Pranay Prabhat, David Flynn ARM, Cambridge, United Kingdom The Internet of Things is widely expected to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). One challenge this poses is energy efficiency, as it will prove cost-prohibitive to regularly replace billions of batteries. Node cost is another concern, which will demand ever-greater integration. Ease of SW development must also remain a priority to HW designers. Addressing all of the above, this paper presents an 11.7pJ/cycle subthreshold WSN processing sub-system implemented in low-leakage 65nm CMOS, scalable from 850nW active power at 250mV to 66MHz at 900mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80nW CPU and RAM state-retention power gating for SW-transparent leakage reduction. The research SoC (Fig. 8.1.1) features 3 independent sub-systems implemented

👥 作者与机构

James Myers, Anand Savanth, David Howard, Rohan Gaddh,