Multi-Standard 185fsrms 0.3-to-28Gb/s 40dB Backplane Signal Conditioner with Adaptive Pattern-Match 36-Tap DFE and Data-Rate-Adjustment PLL in 28nm CMOS

📋 论文概要

本文提出一种多标准背板信号调理器，采用自适应模式匹配的36抽头判决反馈均衡器，支持0.3至28Gb/s的数据速率，并实现185fsrms的低抖动和40dB的信道损耗补偿。

💡 主要创新点

• 提出多标准自适应信号调理架构，覆盖0.3-28Gb/s宽数据速率范围。
• 采用自适应模式匹配的36抽头DFE，通过优化抽头系数有效消除码间干扰和反射。
• 通过减少抽头系数求和延迟，提升均衡器收敛速度与精度。

🏷 关键词

📄 原文摘要

Norio Nakajima2, Masatoshi Tsuge2, Tatsunori Usugi2, Tomofumi Hokari2, Hideki Koba2, Takemasa Komori2, Junya Nasu2, Tsuneo Kawamata2, Yuichi Ito2, Seiichi Umai2, Jun Kumazawa2, Hiroaki Kurahashi2, Takashi Muto2, Takeo Yamashita2, Masatoshi Hasegawa2, Keiichi Higeta2 Hitachi, Tokyo, Japan, Hitachi, Kanagawa, Japan 1 2 be cancelled sufficiently. To reduce this delay, the summed current of tap coefficients 3 to 36 (H3 to H36) are added to the data. Second, if the tap coefficients are not accurate, the ISI and reflections cannot be cancelled sufficiently. To optimize the tap coefficients, it is necessary to fix the CDR lock-point and balance tap coefficients between data patterns. For a long trace channel, a data edge is affected by the data pattern due to residual ISI. The transitions in the Nyquist patterns of 01 and 10 may not cross over the threshold voltage (+/-W) due to a lack of equalization. Thus, the CDR cannot use these

👥 作者与机构

Takashi Kawamoto1, Takayasu Norimatsu1, Kenji Kogo1, Fumio Yuki1,