A 409GOPS/W Adaptive and Resilient Domino Register File in 22nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection

📋 论文概要

该论文提出了一种在22nm Tri-Gate CMOS工艺中实现的自适应和弹性多米诺寄存器文件，通过原位时序裕度和错误容忍技术，有效应对工艺变化、电压降、温度和老化问题，实现了409GOPS/W的高能效。

💡 主要创新点

• 提出自适应时序裕度技术，动态调整寄存器文件的工作点以优化能效。
• 引入错误容忍机制，允许在时序违规时进行错误恢复，提高可靠性。
• 采用22nm Tri-Gate CMOS工艺，结合多米诺读路径和静态差分写，实现高性能与低功耗的平衡。

🏷 关键词

📄 原文摘要

Droop, Temperature and Aging Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo Aseron, Trang Nguyen Jr, Charles Augustine, James Tschanz, Vivek De Intel, Hillsboro, OR 8-transistor (8T) cell 1-read/1-write (1R1W) register files (RF) with domino read and static differential write are critical performance-limiting building blocks in high-performance microprocessor datapaths. The RF operating voltage (V) and frequency (F) are limited by the delay of the precharge-evaluate read critical path. Traditionally, the operating V/F is set to ensure no read timing error across all data access patterns in the RF array in the presence of within-die (WID) parameter (P) variations, and worst-case voltage droops, temperature (T) changes and transistor-aging-induced delay degradations. However, many of these worst-case conditions and events are rare during normal operation. Therefore, these V/F guardbands can severely limit the best-achievable

👥 作者与机构

for Tolerance to Within-Die Variation, Voltage