A Sub-Sampling All-Digital Fractional-N Frequency Synthesizer with -111dBc/Hz In-Band Phase Noise and an FOM of -242dB

📋 论文概要

本文提出了一种采用亚采样技术的全数字分数-N频率合成器，解决了传统TDC分辨率限制导致的ADPLL噪声性能差的问题。实现了-111dBc/Hz的带内相位噪声和-242dB的FOM。

💡 主要创新点

• 采用亚采样技术替代传统TDC，提高了时间分辨率，降低了带内相位噪声。
• 全数字架构，避免了模拟电路的非理想性，适用于先进工艺。

🏷 关键词

📄 原文摘要

Seyed Arash Mirhaj1, Yen-Cheng Kuan1, Huan-Neng Chen2, Chewn-Pu Jou2, Ming-Hsien Tsai2, Fu-Lung Hsueh2, Mau-Chung Frank Chang1 University of California, Los Angeles, CA, 2TSMC, Hsinchu, Taiwan 1 The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-N ADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL’s high frequency node and converting it into a digital code. This achieves a higher time resolution with less power. Figure 14.9.1 shows the block diagram of the proposed ADPLL. It contains two

👥 作者与机构

Zuow-Zun Chen1, Yen-Hsiang Wang1, Jaewook Shin1, Yan Zhao1,