⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种高度数字化的频率合成器，采用环形振荡器频率-数字转换和噪声消除技术，解决了数字分数N PLL中量化噪声和杂散性能较差的问题。
Digital fractional-N PLLs are increasingly used in place of analog fractional-N PLLs as frequency synthesizers in wireless applications, because they avoid large analog loop filters and can tolerate device leakage and low supply voltages, which makes them better-suited to highly-scaled CMOS technology [1-6]. However, the phase noise and spurious tone performance of previously published digital PLLs is inferior to that of the best analog PLLs. This is because all fractional-N PLLs introduce quantization noise, and in prior digital PLLs this noise has higher power or spurious tones than in comparable analog PLLs. Digital PLLs based on ΔΣ frequency-to-digital conversion (FDC-PLLs) offer a potential solution to this problem in that their quantization noise ideally is equivalent to that of analog PLLs, but prior FDC-PLLs incorporate charge pumps and ADCs that have so far limited their performance and minimum supply
Colin Weltin-Wu1,2, Guobi Zhao2, Ian Galton2
Analog Devices, San Jose, CA, 2University of California, San Diego, CA