A 5.8Gb/s Adaptive Integrating Duobinary-Based DFE Receiver for Multi-Drop Memory Interface

📋 论文概要

该论文提出了一种用于多分支内存接口的5.8Gb/s自适应积分双二进制DFE接收器。通过积分双二进制均衡器结合DFE抽头消除码间干扰，并采用基于SS-LMS的自适应算法实现精确均衡，解决了高速低延迟数据访问中的信号完整性挑战。

💡 主要创新点

• 提出积分双二进制均衡器与DFE结合的结构，通过求和积分器同时处理双二进制信号和DFE抽头信号，有效消除ISI和高频噪声。
• 设计抽头嵌入双二进制解码器，在双二进制到二进制转换过程中嵌入额外DFE抽头，进一步消除残余ISI。
• 采用基于SS-LMS的自适应算法，从双二进制信号中提取转换信息实现准确的自适应均衡。

🏷 关键词

📄 原文摘要

precursor shape and main cursor peak level. The summing integrator then sums and integrates the duobinary equalizer output and signals from DFE taps to generate a duobinary signal free of ISI and high-frequency noise. The tap-embedded duobinary decoder performs the duobinary-to-binary conversion, and embeds another DFE tap for further ISI cancellation. The receiver presents an accurate adaptation based on SS-LMS algorithm by extracting transition information from the duobinary signal. 1 2 Emerging applications like cloud computing require high-speed low-latency access to high-volume data. In these applications, use of memory modules having multi-drop channels may be needed for time-efficient access to highdensity memory data. A key design issue here is how to let interface transceivers

👥 作者与机构

Hyun-Wook Lim1,2, Sung-Won Choi1,2, Sang-Kyu Lee2,

Chang-Hoon Baek2, Jae-Youl Lee2, Gyoo-Cheol Hwang2, Bai-Sun Kong1, Young-Hyun Jun2 Sungkyunkwan University, Suwon, Korea, Samsung Electronics, Hwaseong, Korea relatively identical