A 0.6V 1.17ps PVT-Tolerant and Synthesizable Time-to-Digital Converter Using Stochastic Phase Interpolation with 16× Spatial Redundancy in 14nm FinFET Technology

📋 论文概要

该论文提出了一种基于随机相位插值的时数转换器(TDC)，在0.6V低电压下实现了1.17ps的高分辨率，且具有PVT容忍性和可综合性。它解决了传统TDC因延迟单元变化和失配导致的性能受限问题，同时避免了高功耗和大面积开销。

💡 主要创新点

• 采用随机相位插值技术实现16倍空间插值，在低电压下获得高分辨率。
• 设计具有PVT鲁棒性的电路结构，无需额外误差校正或外部控制。
• 提出可综合的TDC架构，便于在数字设计流程中集成。

🏷 关键词

📄 原文摘要

timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of quantization. Vernier delay-line-based TDCs [1] are a good example. Their performance, however, is limited by delay variation and random mismatch among delay cells, unless additional error correction or external control are applied. A time-domain successive-approximation scheme [2] could be an option to achieve high resolution but it consumes too much power and area to generate precisely tuned delay cells. In another case, time-amplifier-based multi-step TDCs [3,4] that can alleviate the requirement on the minimum unit delay of the quantization by

👥 作者与机构

Sung-Jin Kim, Wooseok Kim, Minyoung Song,

Jihyun Kim, Taeik Kim, Hojin Park Samsung Electronics, Hwaseong, Korea A time-to-digital converter (TDC) is a key element for the digitization of