A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4×-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique

📋 论文概要

该论文提出了一种基于2.6b/cycle架构的10位1.7GS/s 4倍时间交织SAR ADC，采用多步硬件退休技术来降低校准开销和功耗。通过优化单通道效率和交织结构，实现了15.4mW的低功耗和高速度。

💡 主要创新点

• 提出2.6b/cycle架构，相比传统2b/cycle结构提高了转换效率，减少了所需比较器数量。
• 引入多步硬件退休技术，动态关闭冗余硬件，降低功耗并缓解通道间匹配要求。
• 采用4倍时间交织结构，在保持高分辨率的同时实现1.7GS/s的高速转换。

🏷 关键词

📄 原文摘要

(TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching requirements between channels; in some cases, >50% of total power is for calibration purposes [1]. Thus, to realize high-speed and high-resolution ADCs with TI structures, it is important to alleviate the calibration burden by choosing a suitable number of power-efficient high-speed single channels. Previously reported CDAC-based 2b/cycle structures [2-5] made contributions in realizing high-speed single-channel ADCs [2-4] with high resolution [5] by using additional capacitive DACs and modified switching logic. The power overhead and the complexity of the additional logic

👥 作者与机构

Hyeok-Ki Hong1, Hyun-Wook Kang1, Dong-Shin Jo1, Dong-Suk Lee2,

Yong-Sang You2, Yong-Hee Lee2, Ho-Jin Park2, Seung-Tak Ryu1 KAIST, Daejeon, Korea, 2Samsung Electronics, Hwaseong, Korea 1 With the growing interest in time-interleaved